The axi_ad4858 IP core is design as the HDL interface for the AD4858 ADC.
Features:
- AXI based configuration
- LVDS and CMOS support
- Configurable number of active data lines (CMOS - build-time configurable)
- Oversampling support
- Supports packet formats 0,1,2 or 3
- CRC check support
- Real-time data header access
- Channel based raw data access(0x0408)
- Xilinx devices compatible
Documentation at https://wiki.analog.com/resources/fpga/docs/axi_ad4858
The custom interface IP for AD3552R DAC has more operation capabilities:
- 8b register read/write SDR/DDR
- 16b register read/write SDR/DDR
- data stream SDR/DDR ( clk_in/8 or clk_in/4 update rate)
- selectable input source : DMA/ADC/TEST_RAMP
- data out clock(SCLK) has clk_in/8 frequency when the converter is configured and clk_in/2 when the converter is in stream mode
- the IP reference clock (clk_in) can have a maximum frequency of 132MHz
- the IP has multiple device synchronization capability when the DMA is set as an input data source
Signed-off-by: PopPaul2021 <Paul.Pop@analog.com>
The DDS for each channel was synchronized by the main channel.
One problem with this aporoach is that when a user sets a DDS that
is not from the main channel the sinchronization does not happend.
This behavior is not user friendly in IIO-Oscilloscope or within other
configuration methods.
This commit keeps all channels in sync by triggering the sync on all
channels from each individual channel.
Add support for DDS phase width greather than 16.
The software should read the DDS phase data width register and configure
the DDS init and increment registers accordingly, otherwise the obtained
DDS output frequency will not be the desired one for DDS phase width
different than 16.
DDS_incr = (f_out * 2^(phase_width) * clkratio)/f_if
* Removed the commercial JESD license and put the ADIBSD or GPL v2 like
for other Verilog files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
Due to nets being optimized at IP-level during the no-OOC synthesis flow,
constraints related to req_clk (request clock) were not being applied,
causing the design to not meet timing.
The fix considers the synchronous modes, appending the possible resulting
req_clk's names after the synthesis flow.
Due to grounded signals in the DMA_TYPE_SRC != DMA_TYPE_STREAM_AXI config.,
sync_rewind is removed during synthesis, even so, constraints were
trying to be applied to those nets.
To resolve this, sync_rewind block was moved to inside the generate.
Vivado seems to properly suppress "Empty list" warnings when the circuit does not exist because of a generate rule.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
docs/regmap/adi_regmap_adc.txt:
- add softspan to regmap
library/common/up_adc_channel.v
- update copyright year header
- add softspan to regmap
library/common/up_adc_common.v
- update minor version
Signed-off-by: John Erasmus Mari Geronimo <Johnerasmusmari.Geronimo@analog.com>
* ad_data_in: Add new logic and explanations
* Added parameters IDELAY_TYPE, DELAY_FORMAT, US_DELAY_TYPE to be used
with the IDELAY instances
* Added explanations
* Added option to bypass IDELAY if it's not instantiated, regardless of
the FPGA_TECHNOLOGY parameter
* Determined a part of the logic for EN_VTC (by the UG) but not for all
modes since we don't have use cases for them
* Changed logic when adding ODELAY: now you must set IODELAY_ENABLE = 1
and FPGA_TECHNOLOGY != NONE if you want it
* ad_data_out:
* Updated ODDR parameter
* Fixed issue with ODDR inputs D1, D2: D1 must be with _p and D2 with _n,
according to the Xilinx template
* Removed _ES1 from IODELAY_SIM_DEVICE
* Added ODELAY for UltraScale
* Before, there was no support for UltraScale/+, and the output data
was completely disconnected from the ODDR
* The support for this was requested in this issue, although as of now we don't
have a design that uses it: https://github.com/analogdevicesinc/hdl/issues/917
* Added parameters ODELAY_TYPE, DELAY_FORMAT, US_DELAY_TYPE to be used
with the ODELAY instances
* Added explanations
* Added option to bypass ODELAY if it's not instantiated, regardless of
the FPGA_TECHNOLOGY parameter
* Determined a part of the logic for the EN_VTC (by the UG) but not for
all modes since we don't have use cases for them
* Changed logic when adding ODELAY: now you must set IODELAY_ENABLE = 1
and FPGA_TECHNOLOGY != NONE if you want it
---------
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
The SPI Engine cores were named directly inside the script and this
would mean that for multiple SPI Engine instances IPs with the same
name would appear. These updates will introduce the hierarchy name
into the name given to the cores and will therefore allow for
multiple instances of SPI Engine to be added to the same Xilinx
project.
Projects which use spi_engine.tcl will be updated to account for
these changes.
If the sampling clock is lower than dclk*number_of_active_lines*32 the interface should wait for the next adc_ready signal to reset the counter.
The adc_valid_p signal should be set high just for a clock period after the sample was captured.
- Issue introduced by commit 173f4a83d4
- When IODELAY_ENABLE was inserted in axi_adrv9001_if for adrv9001_rx (Xilinx instance),
for Intel instance (intel/adrv9001_rx.v) was omitted and caused a build error for
adrv9001/a10soc
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
Replaced the existing axi_tdd with the new version
* Added DEFAULT_POLARITY synth parameter and RO register
* Added TDD_STATUS register
* Added TDD_SYNC_RST feature
* Used the asy_ prefix for signals which are not synced
* Added logic to force the state from ARMED to RUNNING when startup_delay=0
* Added feature to finish the burst when the module is disabled before its completion
Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
AndreiGrozav
PopPaul2021
Jem Geronimo
Iulia Moldovan
alin724
Jorge Marques
Jem Geronimo
imoldovan
Sergiu Arpadi
laurent-19
Istvan-Zsolt Szekely
Filip Gherman
Ionut Podgoreanu