3 Commits (fd0870352bc69dfdd19f0259a066ef4d59aad036)

Author	SHA1	Message	Date
PopPaul2021	9caa15522a	The memory interconnect was moved from HP0 to HP1 on Coraz7s projects (#1023)	2022-09-29 15:14:57 +03:00
PopPaul2021	8a77d4fb05	coraz7s: Memory interconnect fix (#1014)	2022-09-23 14:58:43 +03:00
sergiu arpadi	0ac49027bd	cn0561_coraz7s: Initial commit ... Because the inferface signals which pass through the eval board's Arduino connector are connected to level shifters the design will not work at the maximum clk frequency of 48MHz. The maximum tested frequency is 24MHz.	2022-05-11 17:30:26 +03:00