Commit Graph

20 Commits (fd81a821b0cdb5213361665d64fc259130682810)

Author SHA1 Message Date
Iulia Moldovan c9a7d4d927 Add copyright and license to .tcl, .ttcl files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 15:22:26 +03:00
Sergiu Arpadi 3241924d14 sysid_intel: Added sysid to intel projects 2020-09-11 15:46:06 +03:00
Istvan Csomortani 8818089015 a10soc: Reconfiguration interface address width improvement
The reconfiguration interface's address width is different in various
architectures. Define the required address width in system_qsys.tcl.
2020-09-09 14:15:37 +03:00
Istvan Csomortani 9043f3737b Revert "a10gx: Optimise the base design"
This reverts commit 9afc871b70.
2020-08-11 10:14:18 +03:00
Istvan Csomortani 4af0c98c56 a10gx: Fix exceptionSlave interface definition for HPS 2020-08-11 10:14:18 +03:00
Istvan Csomortani 0b51c474a1 a10gx: Add a Avalon Pipeline Bridge between EMIF and DMA's 2020-08-11 10:14:18 +03:00
Istvan Csomortani 9afc871b70 a10gx: Optimise the base design
Add a clock crossing bridge for the interfaces that runs on a different
clock than the emif_user_clk.

This way we can simplify the main interconnect, and prevent occasional
timing violations.
2019-06-04 11:28:37 +03:00
STEVE KRAVATSKY ee01ea3736 daq2/a10gx: Add cfi_flash to qsys
+ Add cfi_flash to qsys
   + Set nios reset vector to cfi_flash
2017-10-04 11:30:29 +01:00
AndreiGrozav 3a47567f9c common/a10gx: Chance SPI frequency from 128KHz to 10 MHz 2017-09-19 18:01:18 +03:00
Adrian Costina 5a98e727f2 A10GX: Update DDR3 configuration 2017-07-27 12:38:14 +01:00
Rejeesh Kutty 0bd22e78d9 altera- adi-project-create version 2017-06-05 15:24:35 -04:00
Rejeesh Kutty cfcb269d38 a10gx- change ddr to 1G 2017-05-15 09:32:36 -04:00
Rejeesh Kutty ebeebdddf0 altera- infer latest versions 2017-05-12 13:40:14 -04:00
Rejeesh Kutty c728299e71 altera- default to latest version 2017-05-12 13:25:17 -04:00
Rejeesh Kutty 50552ce7d6 adrv9371x- altera updates 2016-10-27 09:25:00 -04:00
Adrian Costina 0d095f5da9 a10gx: Added system_type variable in common design 2016-09-08 11:29:14 +03:00
Rejeesh Kutty c6f4def93d altera- make mmu a make switch 2016-08-08 11:54:51 -04:00
Adrian Costina 52ae3ddd6c a10gx: Updated common files to 16.0 2016-08-01 15:08:12 +03:00
Adrian Costina c6c3622816 a10gx: Updated common design adding explicit clock frequency and synchronous reset deassertion 2016-06-30 10:59:29 +03:00
Rejeesh Kutty 3516ec28b7 daq2/a10gx- qsys updates 2016-06-07 12:28:04 -04:00