Commit Graph

5 Commits (ff7b8ef6ae0a9b524c386f8854c7102d0941e83c)

Author SHA1 Message Date
Iulia Moldovan 0590a4046c Add copyright & license for all files needing ADI JESD specific license
* Added every year when the file was edited, with comma
 * Range if it's consecutive years

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-09-07 10:45:49 +03:00
Iulia Moldovan 0c0617d49e libraries: Update modules according to guideline
* Added header license for the files that didn't have
* Modified parentheses
* Removed extra spaces at the end of lines
* Fixed parameters list to be each parameter on its line
* Deleted lines after endmodule and consecutive empty lines
* Fixed indentation

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
Lars-Peter Clausen d72fac4b1e Add missing timescale annotations
For consistent simulation behavior it is recommended to annotate all source
files with a timescale. Add it to those where it is currently missing.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-10-17 10:32:47 +03:00
Lars-Peter Clausen c514c5cc28 jesd204_soft_pcs_loopback_tb: Add parameter for lane polarity inversion
Add a parameter to the soft_pcs_loopback_tb that allows to test whether the
soft PCS modules work correctly when the lane polarity is inverted.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-02 09:37:23 +02:00
Lars-Peter Clausen 4df841addc jesd204: Add soft logic PCS
Add soft logic PCS that performs 8b10b encoding for TX and character
pattern alignment and 8b10b decoding for RX.

The modules are intended to be used in combination with a transceiver that
does not have these features implemented in hard logic PCS.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-21 11:09:42 +02:00