TITLE I3C Controller (i3c_controller_host_interface) i3c_controller_host_interface ENDTITLE ############################################################################################ ############################################################################################ REG 0x00 VERSION Version of the peripheral. Follows semantic versioning. Current version 0.01.00 ENDREG FIELD [31:16] 0x00 VERSION_MAJOR RO ENDFIELD FIELD [15:8] 0x01 VERSION_MINOR RO ENDFIELD FIELD [7:0] 0x00 VERSION_PATCH RO ENDFIELD ############################################################################################ ############################################################################################ REG 0x01 DEVICE_ID ENDREG FIELD [31:0] ''ID'' DEVICE_ID RO Value of the ID configuration parameter. ENDFIELD ############################################################################################ ############################################################################################ REG 0x02 SCRATCH ENDREG FIELD [31:0] 0x00000000 SCRATCH RW Scratch register useful for debug. ENDFIELD ############################################################################################ ############################################################################################ REG 0x10 ENABLE ENDREG FIELD [0] 0x1 ENABLE RW Enable register. If the enable bit is set to 1 the internal state of the peripheral is reset. For proper operation, the bit needs to be set to 0. ENDFIELD ############################################################################################ ############################################################################################ REG 0x20 IRQ_MASK ENDREG FIELD [7] 0x0 DAA_PENDING RW If set to 0 the DAA_PENDING interrupt is masked. ENDFIELD FIELD [6] 0x0 IBI_PENDING RW If set to 0 the IBI_PENDING interrupt is masked. ENDFIELD FIELD [5] 0x0 CMDR_PENDING RW If set to 0 the CMDR_PENDING interrupt is masked. ENDFIELD FIELD [4] 0x0 IBI_ALMOST_FULL RW If set to 0 the IBI_ALMOST_FULL interrupt is masked. ENDFIELD FIELD [3] 0x0 SDI_ALMOST_FULL RW If set to 0 the SDI_ALMOST_FULL interrupt is masked. ENDFIELD FIELD [2] 0x0 SDO_ALMOST_EMPTY RW If set to 0 the SDO_ALMOST_EMPTY interrupt is masked. ENDFIELD FIELD [1] 0x0 CMDR_ALMOST_FULL RW If set to 0 the CMDR_ALMOST_FULL interrupt is masked. ENDFIELD FIELD [0] 0x0 CMD_ALMOST_EMPTY RW If set to 0 the CMD_ALMOST_EMPTY interrupt is masked. ENDFIELD ############################################################################################ ############################################################################################ REG 0x21 IRQ_PENDING ENDREG FIELD [31:0] 0x00000000 IRQ_PENDING RW Pending IRQs with mask. Write 1 at the CMDR_PENDING bit to clear it. For CMDR_PENDING and IBI_PENDING, will be cleared if the FIFOs are also empty. For DAA_PENDING, will be cleared if the SDO FIFO is not empty, that means, got dynamic address in the pipeline. ENDFIELD ############################################################################################ ############################################################################################ REG 0x22 IRQ_SOURCE ENDREG FIELD [31:0] 0x00000000 IRQ_SOURCE RO Pending IRQs without mask. ENDFIELD ############################################################################################ ############################################################################################ REG 0x30 CMD_FIFO_ROOM ENDREG FIELD [31:0] 0xXXXXXXXX CMD_FIFO_ROOM RO Number of free entries in the CMD FIFO. ENDFIELD ############################################################################################ ############################################################################################ REG 0x31 CMDR_FIFO_LEVEL ENDREG FIELD [31:0] 0x00000000 CMDR_FIFO_LEVEL RO Number of valid entries in the CMDR FIFO. ENDFIELD ############################################################################################ ############################################################################################ REG 0x32 SDO_FIFO_ROOM ENDREG FIELD [31:0] 0xXXXXXXXX SDO_FIFO_ROOM RO Number of free entries in the SDO FIFO. ENDFIELD ############################################################################################ ############################################################################################ REG 0x33 SDI_FIFO_LEVEL ENDREG FIELD [31:0] 0x00000000 SDI_FIFO_LEVEL RO Number of valid entries in the serial-data-in FIFO. ENDFIELD ############################################################################################ ############################################################################################ REG 0x34 IBI_FIFO_LEVEL ENDREG FIELD [31:0] 0x00000000 IBI_FIFO_LEVEL RO Number of valid entries in the in-bus-interrupt FIFO. ENDFIELD ############################################################################################ ############################################################################################ REG 0x35 CMD_FIFO Command FIFO register. Writing to this register inserts an entry into the CMD FIFO. Writing to this register when the CMD FIFO is full has no effect and the written entry is discarded. Reading from this register always returns 0x00000000. The Software is responsive for a valid sequence of commands. If the peripheral does not ACK when required during a command, the procedure exits and the next command in the FIFO is interpreted. See :ref:`i3c_controller instruction-format` for the structure of the command. ENDREG FIELD [22] 0xX CMD_IS_CCC WO Indicate if it is a CCC transfer (1) or not (0). ENDFIELD FIELD [21] 0xX CMD_BCAST_HEADER WO Include broadcast header in private transfer (1) or not (0). ENDFIELD FIELD [20] 0xX CMD_SR WO Repeated start flag, yield a Sr (1) or P (0) at the end of the transfer. ENDFIELD FIELD [19:8] 0xXXX CMD_BUFFER_LENGHT WO Unsigned 12-bits payload length, direction depends on RNW value. ENDFIELD FIELD [7:1] 0xXX CMD_DA WO 7-bit device address (don’t care in broadcast mode). ENDFIELD FIELD [0] 0xX CMD_RNW WO If should retrieve data from device (1) or not (0). ENDFIELD ############################################################################################ ############################################################################################ REG 0x36 CMDR_FIFO CMDR FIFO register. Reading from this register removes the first entry from the CMDR FIFO. Reading this register when the CMDR FIFO is empty will return undefined data. Writing to it has no effect. ENDREG FIELD [23:0] 0x?? CMDR_FIFO_ERROR RO If an error occurred during the transfer. ENDFIELD FIELD [19:8] 0x?? CMDR_FIFO_BUFFER_LENGTH RO Unsigned 12-bits transferred payload length. ENDFIELD FIELD [7:0] 0x?? CMDR_FIFO_SYNC RO Command synchronization. ENDFIELD ############################################################################################ ############################################################################################ REG 0x37 SDO_FIFO SDO FIFO register. Writing to this register inserts an entry into the SDO FIFO. Writing to this register when the SDO FIFO is full has no effect and the written entry is discarded. Reading from this register always returns 0x00000000. ENDREG FIELD [31:24] 0xXX SDO_FIFO_BYTE_3 RO ENDFIELD FIELD [23:16] 0xXX SDO_FIFO_BYTE_2 RO ENDFIELD FIELD [15:8] 0xXX SDO_FIFO_BYTE_1 RO ENDFIELD FIELD [7:0] 0xXX SDO_FIFO_BYTE_0 RO ENDFIELD ############################################################################################ ############################################################################################ REG 0x38 SDI_FIFO SDI FIFO register. Reading from this register removes the first entry from the SDI FIFO. Reading this register when the SDI FIFO is empty will return undefined data. Writing to it has no effect. ENDREG FIELD [31:0] 0xXXXXXXXX SDI_FIFO RO ENDFIELD ############################################################################################ ############################################################################################ REG 0x39 IBI_FIFO IBI FIFO register. Reading from this register removes the first entry from the IBI FIFO. Reading this register when the IBI FIFO is empty will return undefined data. Writing to it has no effect. ENDREG FIELD [23:17] 0xXX IBI_FIFO_DA RO IBI Dynamic address. ENDFIELD FIELD [15:8] 0xXX IBI_FIFO_MDB RO IBI MDB, if the peripheral's BCR[2] is Low, the field is ignored. ENDFIELD FIELD [7:0] 0xXX IBI_FIFO_SYNC RO Synchronization number. ENDFIELD ############################################################################################ ############################################################################################ REG 0x3a FIFO_STATUS ENDREG FIELD [2] 0x1 SDI_EMPTY RO If there is no element to be read in the SDI FIFO. ENDFIELD FIELD [1] 0x1 IBI_EMPTY RO If there is no element to be read in the IBI FIFO. ENDFIELD FIELD [0] 0x1 CMDR_EMPTY RO If there is no element to be read in the CMDR FIFO. ENDFIELD ############################################################################################ ############################################################################################ REG 0x40 OPS Configure the operation of the controller. ENDREG FIELD [7] 0x0 OPS_STATUS_NOP RO This bit is set to 1 when the bus is not executing any procedure. It is not idle bus condition since it set right after the Stop. ENDFIELD FIELD [6:5] 0x0 OPS_SPEED_GRADE RW Sets the speed grade in push-pull mode. Speed with 100MHz driver clock are: 00: 1.56MHz (default) 01: 3.12MHz 10: 6.25MHz 11: 12.50MHz ENDFIELD FIELD [4:1] 0x0 OPS_OFFLOAD_LENGTH RW Offload commands length. ENDFIELD FIELD [0] 0x0 OPS_MODE RW Set 0 to direct transfers, 1 to offload operation. ENDFIELD ############################################################################################ ############################################################################################ REG 0x50 IBI_CONFIG Configure the In-Band Interrupt (IBI) feature. ENDREG FIELD [1] 0x0 IBI_CONFIG_LISTEN WO Set this bit to listen for IBI requests (when a peripheral pulls SDA Low during bus available). After the IBI request is resolved, the controller returns to idle, since it is was not doing a cmd transfer. This should be set to 1 during normal operation, even if IBI_CONFIG_ENABLE is disabled. ENDFIELD FIELD [0] 0x0 IBI_CONFIG_ENABLE WO Set this bit to accept (ACK) IBI requests. If disabled, the controller will NACK IBI requests. If enabled, the controller will ACK the IBI request and receive the MDB. In both cases, the controller will proceed with the cmd transfer after resolving the IBI request, if any. Accepted IBIs fill the IBI_FIFO and generate an interrupt to the PS. IBI_CONFIG_LISTEN set to 1 and IBI_CONFIG_ENABLE set to 0 ensures that incoming IBIs are rejected as they come. ENDFIELD ############################################################################################ ############################################################################################ REG 0x60 DEV_CHAR Holds devices characteristics that are looked-up during execution. The content is written only by software. To read an address, write the address with DEV_CHAR_0_WEN 0 and then read. ENDREG FIELD [15:9] 0x00 DEV_CHAR_ADDR RW Device address to apply DEV_CHAR[3:0]. ENDFIELD FIELD [8] 0xX DEV_CHAR_WEN W Enable write of the fields. ENDFIELD FIELD [3] 0x0 DEV_CHAR_HAS_IBI_PAYLOAD RW Indicates if the device sends at least MDB during the IBI. 0 does not, 1 does. ENDFIELD FIELD [2] 0x0 DEV_CHAR_IS_IBI_CAPABLE RW Indicates if the device can send IBI. 0 does not, 1 does. ENDFIELD FIELD [1] 0x0 DEV_CHAR_IS_ATTACHED RW Indicate if the device is attached. ENDFIELD [0] 0x0 DEV_CHAR_IS_I2C RW Indicates if the device is I²C. 0 is I3C device, 1 is I²C device. ENDFIELD ############################################################################################ ############################################################################################ REG 0xb0 + 0x01*n WHERE n IS FROM 0 TO 15 OFFLOAD_CMD_n Offload command memory. Write commands in sequence to these addresses and update the OFFLOAD_CMD_LENGTH register. ENDREG FIELD [31:0] 0x00 OFFLOAD_CMD RW The command to the I3C controller to execute. ENDFIELD ############################################################################################ ############################################################################################ REG 0xc0 + 0x01*n WHERE n IS FROM 0 TO 15 OFFLOAD_SDO_n Offload SDO memory. Dual access memory sector used to store the SDO payload for the offload execution. The SDO is read by the parsing the OFFLOAD_CMD commands. For example, if the first command on OFFLOAD_CMD is a write with length 3 and the next with length 2, 3 bytes from OFFLOAD_SDO_0 are sent, then 2 bytes from OFFLOAD_SDO_1 are sent. If OPS_OFFLOAD_LENGTH is 2, then the burst concludes and the "pointer" resets to OFFLOAD_SDO_0, otherwise, the execution continues until all commands are resolved, always bounded by OPS_OFFLOAD_LENGTH. ENDREG FIELD [31:24] 0x00 OFFLOAD_SDO_BYTE_3 RO ENDFIELD FIELD [23:16] 0x00 OFFLOAD_SDO_BYTE_2 RO ENDFIELD FIELD [15:8] 0x00 OFFLOAD_SDO_BYTE_1 RO ENDFIELD FIELD [7:0] 0x00 OFFLOAD_SDO_BYTE_0 RO ENDFIELD ############################################################################################ ############################################################################################