// *************************************************************************** // *************************************************************************** // Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. // // Each core or library found in this collection may have its own licensing terms. // The user should keep this in in mind while exploring these cores. // // Redistribution and use in source and binary forms, // with or without modification of this file, are permitted under the terms of either // (at the option of the user): // // 1. The GNU General Public License version 2 as published by the // Free Software Foundation, which can be found in the top level directory, or at: // https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html // // OR // // 2. An ADI specific BSD license as noted in the top level directory, or on-line at: // https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE // // *************************************************************************** // *************************************************************************** `timescale 1ns/100ps module system_top ( inout [14:0] ddr_addr, inout [ 2:0] ddr_ba, inout ddr_cas_n, inout ddr_ck_n, inout ddr_ck_p, inout ddr_cke, inout ddr_cs_n, inout [ 3:0] ddr_dm, inout [31:0] ddr_dq, inout [ 3:0] ddr_dqs_n, inout [ 3:0] ddr_dqs_p, inout ddr_odt, inout ddr_ras_n, inout ddr_reset_n, inout ddr_we_n, inout fixed_io_ddr_vrn, inout fixed_io_ddr_vrp, inout [53:0] fixed_io_mio, inout fixed_io_ps_clk, inout fixed_io_ps_porb, inout fixed_io_ps_srstb, inout iic_scl, inout iic_sda, input rx_clk_in_p, input rx_clk_in_n, input rx_frame_in_p, input rx_frame_in_n, input [ 5:0] rx_data_in_p, input [ 5:0] rx_data_in_n, output tx_clk_out_p, output tx_clk_out_n, output tx_frame_out_p, output tx_frame_out_n, output [ 5:0] tx_data_out_p, output [ 5:0] tx_data_out_n, output enable, output txnrx, input clkout_in, inout gpio_clksel, inout gpio_resetb, inout gpio_sync, inout gpio_en_agc, inout [ 3:0] gpio_ctl, inout [ 7:0] gpio_status, output spi_csn, output spi_clk, output spi_mosi, input spi_miso, input pcie_rstn, inout pcie_waken, input pcie_ref_clk_p, input pcie_ref_clk_n, input [ 3:0] pcie_data_rx_p, input [ 3:0] pcie_data_rx_n, output [ 3:0] pcie_data_tx_p, output [ 3:0] pcie_data_tx_n, output pcie_reset_done); // internal registers reg pcie_reset_done_int = 1'b0; // internal signals wire pcie_ref_clk; wire pcie_clk; wire pcie_rst; wire [63:0] gpio_i; wire [63:0] gpio_o; wire [63:0] gpio_t; // assignments assign pcie_waken = 1'bz; assign pcie_reset_done = pcie_reset_done_int; // PCIe reset monitor always @(posedge pcie_clk or posedge pcie_rst) begin if (pcie_rst == 1'b1) begin pcie_reset_done_int <= 1'b0; end else begin pcie_reset_done_int <= 1'b1; end end // instantiations IBUFDS_GTE2 i_ibufds_pcie_ref_clk ( .CEB (1'd0), .I (pcie_ref_clk_p), .IB (pcie_ref_clk_n), .O (pcie_ref_clk), .ODIV2 ()); ad_iobuf #(.DATA_WIDTH(16)) i_iobuf ( .dio_t ({gpio_t[51], gpio_t[46:32]}), .dio_i ({gpio_o[51], gpio_o[46:32]}), .dio_o ({gpio_i[51], gpio_i[46:32]}), .dio_p ({ gpio_clksel, // 51:51 gpio_resetb, // 46:46 gpio_sync, // 45:45 gpio_en_agc, // 44:44 gpio_ctl, // 43:40 gpio_status})); // 39:32 system_wrapper i_system_wrapper ( .ddr_addr (ddr_addr), .ddr_ba (ddr_ba), .ddr_cas_n (ddr_cas_n), .ddr_ck_n (ddr_ck_n), .ddr_ck_p (ddr_ck_p), .ddr_cke (ddr_cke), .ddr_cs_n (ddr_cs_n), .ddr_dm (ddr_dm), .ddr_dq (ddr_dq), .ddr_dqs_n (ddr_dqs_n), .ddr_dqs_p (ddr_dqs_p), .ddr_odt (ddr_odt), .ddr_ras_n (ddr_ras_n), .ddr_reset_n (ddr_reset_n), .ddr_we_n (ddr_we_n), .enable (enable), .fixed_io_ddr_vrn (fixed_io_ddr_vrn), .fixed_io_ddr_vrp (fixed_io_ddr_vrp), .fixed_io_mio (fixed_io_mio), .fixed_io_ps_clk (fixed_io_ps_clk), .fixed_io_ps_porb (fixed_io_ps_porb), .fixed_io_ps_srstb (fixed_io_ps_srstb), .gpio_i ({63'd0, pcie_reset_done_int}), .gpio_o (), .gpio_t (), .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), .otg_vbusoc (1'b0), .pcie_clk (pcie_clk), .pcie_data_rxn (pcie_data_rx_n), .pcie_data_rxp (pcie_data_rx_p), .pcie_data_txn (pcie_data_tx_n), .pcie_data_txp (pcie_data_tx_p), .pcie_ref_clk (pcie_ref_clk), .pcie_rst (pcie_rst), .pcie_rstn (pcie_rstn), .pl_gpio0_i (gpio_i[31:0]), .pl_gpio0_o (gpio_o[31:0]), .pl_gpio0_t (gpio_t[31:0]), .pl_gpio1_i (gpio_i[63:32]), .pl_gpio1_o (gpio_o[63:32]), .pl_gpio1_t (gpio_t[63:32]), .pl_spi_clk_i (spi_clk), .pl_spi_clk_o (spi_clk), .pl_spi_csn_i (spi_csn), .pl_spi_csn_o (spi_csn), .pl_spi_sdi_i (spi_miso), .pl_spi_sdo_i (spi_mosi), .pl_spi_sdo_o (spi_mosi), .ps_intr_00 (1'b0), .ps_intr_01 (1'b0), .ps_intr_02 (1'b0), .ps_intr_03 (1'b0), .ps_intr_04 (1'b0), .ps_intr_05 (1'b0), .ps_intr_06 (1'b0), .ps_intr_07 (1'b0), .ps_intr_08 (1'b0), .ps_intr_09 (1'b0), .ps_intr_10 (1'b0), .ps_intr_11 (1'b0), .ps_intr_15 (1'b0), .rx_clk_in_n (rx_clk_in_n), .rx_clk_in_p (rx_clk_in_p), .rx_data_in_n (rx_data_in_n), .rx_data_in_p (rx_data_in_p), .rx_frame_in_n (rx_frame_in_n), .rx_frame_in_p (rx_frame_in_p), .spi0_clk_i (1'b0), .spi0_clk_o (), .spi0_csn_0_o (), .spi0_csn_1_o (), .spi0_csn_2_o (), .spi0_csn_i (1'b1), .spi0_sdi_i (1'b0), .spi0_sdo_i (1'b0), .spi0_sdo_o (), .spi1_clk_i (1'b0), .spi1_clk_o (), .spi1_csn_0_o (), .spi1_csn_1_o (), .spi1_csn_2_o (), .spi1_csn_i (1'b1), .spi1_sdi_i (1'b0), .spi1_sdo_i (1'b0), .spi1_sdo_o (), .tdd_sync_i (1'b0), .tdd_sync_o (), .tdd_sync_t (), .tx_clk_out_n (tx_clk_out_n), .tx_clk_out_p (tx_clk_out_p), .tx_data_out_n (tx_data_out_n), .tx_data_out_p (tx_data_out_p), .tx_frame_out_n (tx_frame_out_n), .tx_frame_out_p (tx_frame_out_p), .txnrx (txnrx), .up_enable (gpio_o[47]), .up_txnrx (gpio_o[48])); endmodule // *************************************************************************** // ***************************************************************************