####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################

LIBRARY_NAME := axi_jesd204_tx

GENERIC_DEPS += ../../common/up_axi.v
GENERIC_DEPS += axi_jesd204_tx.v
GENERIC_DEPS += jesd204_up_tx.v

XILINX_DEPS += axi_jesd204_tx_constr.xdc
XILINX_DEPS += axi_jesd204_tx_ip.tcl

XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ctrl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ctrl_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_event.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_event_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_status.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_status_rtl.xml

XILINX_LIB_DEPS += jesd204/axi_jesd204_common

XILINX_INTERFACE_DEPS += jesd204/interfaces

ALTERA_DEPS += ../../altera/common/up_clock_mon_constr.sdc
ALTERA_DEPS += ../../common/up_clock_mon.v
ALTERA_DEPS += ../../util_cdc/sync_bits.v
ALTERA_DEPS += ../../util_cdc/sync_data.v
ALTERA_DEPS += ../../util_cdc/sync_event.v
ALTERA_DEPS += ../axi_jesd204_common/jesd204_up_common.v
ALTERA_DEPS += ../axi_jesd204_common/jesd204_up_sysref.v
ALTERA_DEPS += axi_jesd204_tx_constr.sdc
ALTERA_DEPS += axi_jesd204_tx_hw.tcl

include ../../scripts/library.mk