####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################

PROJECT_NAME := daq2_a10soc

M_DEPS += ../common/daq2_spi.v
M_DEPS += ../common/daq2_qsys.tcl
M_DEPS += ../../common/a10soc/a10soc_system_qsys.tcl
M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl
M_DEPS += ../../common/a10soc/a10soc_plddr4_dacfifo_qsys.tcl
M_DEPS += ../../common/a10soc/a10soc_plddr4_assign.tcl
M_DEPS += ../../../library/altera/adi_jesd204/adi_jesd204_hw.tcl
M_DEPS += ../../../library/altera/avl_dacfifo/avl_dacfifo.v
M_DEPS += ../../../library/altera/avl_dacfifo/avl_dacfifo_byteenable_coder.v
M_DEPS += ../../../library/altera/avl_dacfifo/avl_dacfifo_byteenable_decoder.v
M_DEPS += ../../../library/altera/avl_dacfifo/avl_dacfifo_constr.sdc
M_DEPS += ../../../library/altera/avl_dacfifo/avl_dacfifo_hw.tcl
M_DEPS += ../../../library/altera/avl_dacfifo/avl_dacfifo_rd.v
M_DEPS += ../../../library/altera/avl_dacfifo/avl_dacfifo_wr.v
M_DEPS += ../../../library/altera/avl_dacfifo/util_dacfifo_bypass.v
M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr.v
M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_up.v
M_DEPS += ../../../library/altera/common/ad_mul.v
M_DEPS += ../../../library/altera/common/up_clock_mon_constr.sdc
M_DEPS += ../../../library/altera/common/up_rst_constr.sdc
M_DEPS += ../../../library/altera/common/up_xfer_cntrl_constr.sdc
M_DEPS += ../../../library/altera/common/up_xfer_status_constr.sdc
M_DEPS += ../../../library/altera/jesd204_phy/jesd204_phy_glue.v
M_DEPS += ../../../library/altera/jesd204_phy/jesd204_phy_glue_hw.tcl
M_DEPS += ../../../library/altera/jesd204_phy/jesd204_phy_hw.tcl
M_DEPS += ../../../library/axi_ad9144/axi_ad9144.v
M_DEPS += ../../../library/axi_ad9144/axi_ad9144_channel.v
M_DEPS += ../../../library/axi_ad9144/axi_ad9144_core.v
M_DEPS += ../../../library/axi_ad9144/axi_ad9144_hw.tcl
M_DEPS += ../../../library/axi_ad9144/axi_ad9144_if.v
M_DEPS += ../../../library/axi_ad9680/axi_ad9680.v
M_DEPS += ../../../library/axi_ad9680/axi_ad9680_channel.v
M_DEPS += ../../../library/axi_ad9680/axi_ad9680_hw.tcl
M_DEPS += ../../../library/axi_ad9680/axi_ad9680_if.v
M_DEPS += ../../../library/axi_ad9680/axi_ad9680_pnmon.v
M_DEPS += ../../../library/axi_dmac/2d_transfer.v
M_DEPS += ../../../library/axi_dmac/address_generator.v
M_DEPS += ../../../library/axi_dmac/axi_dmac.v
M_DEPS += ../../../library/axi_dmac/axi_dmac_constr.sdc
M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
M_DEPS += ../../../library/axi_dmac/data_mover.v
M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
M_DEPS += ../../../library/axi_dmac/inc_id.h
M_DEPS += ../../../library/axi_dmac/request_arb.v
M_DEPS += ../../../library/axi_dmac/request_generator.v
M_DEPS += ../../../library/axi_dmac/resp.h
M_DEPS += ../../../library/axi_dmac/response_generator.v
M_DEPS += ../../../library/axi_dmac/response_handler.v
M_DEPS += ../../../library/axi_dmac/splitter.v
M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
M_DEPS += ../../../library/common/ad_axis_inf_rx.v
M_DEPS += ../../../library/common/ad_b2g.v
M_DEPS += ../../../library/common/ad_datafmt.v
M_DEPS += ../../../library/common/ad_dds.v
M_DEPS += ../../../library/common/ad_dds_1.v
M_DEPS += ../../../library/common/ad_dds_sine.v
M_DEPS += ../../../library/common/ad_g2b.v
M_DEPS += ../../../library/common/ad_mem.v
M_DEPS += ../../../library/common/ad_pnmon.v
M_DEPS += ../../../library/common/ad_rst.v
M_DEPS += ../../../library/common/ad_xcvr_rx_if.v
M_DEPS += ../../../library/common/up_adc_channel.v
M_DEPS += ../../../library/common/up_adc_common.v
M_DEPS += ../../../library/common/up_axi.v
M_DEPS += ../../../library/common/up_clock_mon.v
M_DEPS += ../../../library/common/up_dac_channel.v
M_DEPS += ../../../library/common/up_dac_common.v
M_DEPS += ../../../library/common/up_xfer_cntrl.v
M_DEPS += ../../../library/common/up_xfer_status.v
M_DEPS += ../../../library/common/util_delay.v
M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_rx/8b10b_decoder.v
M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v
M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl
M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_rx/pattern_align.v
M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_tx/8b10b_encoder.v
M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v
M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl
M_DEPS += ../../../library/scripts/adi_env.tcl
M_DEPS += ../../../library/scripts/adi_ip_alt.tcl
M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
M_DEPS += ../../../library/util_adcfifo/util_adcfifo_constr.sdc
M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
M_DEPS += ../../../library/util_axis_fifo/address_gray.v
M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
M_DEPS += ../../../library/util_axis_fifo/address_sync.v
M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
M_DEPS += ../../../library/util_cdc/sync_bits.v
M_DEPS += ../../../library/util_cdc/sync_gray.v
M_DEPS += ../../../library/util_cpack/util_cpack.v
M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
M_DEPS += ../../../library/util_upack/util_upack.v
M_DEPS += ../../../library/util_upack/util_upack_dmx.v
M_DEPS += ../../../library/util_upack/util_upack_dsf.v
M_DEPS += ../../../library/util_upack/util_upack_hw.tcl

include ../../scripts/project-altera.mk