// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
// 
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// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// serial data output interface: serdes(x8) or oddr(x2) output module

`timescale 1ps/1ps

module ad_serdes_clk (

  // clock and divided clock

  mmcm_rst,
  clk_in_p,
  clk_in_n,

  clk,
  div_clk,

  // drp interface

  drp_clk,
  drp_rst,
  drp_sel,
  drp_wr,
  drp_addr,
  drp_wdata,
  drp_rdata,
  drp_ready,
  drp_locked);

  // parameters

  parameter   SERDES = 1;
  parameter   MMCM = 1;
  parameter   MMCM_DEVICE_TYPE = 0;
  parameter   MMCM_CLKIN_PERIOD  = 1.667;
  parameter   MMCM_VCO_DIV  = 6;
  parameter   MMCM_VCO_MUL = 12.000;
  parameter   MMCM_CLK0_DIV = 2.000;
  parameter   MMCM_CLK1_DIV = 6;

  // clock and divided clock

  input           mmcm_rst;
  input           clk_in_p;
  input           clk_in_n;

  output          clk;
  output          div_clk;

  // drp interface

  input           drp_clk;
  input           drp_rst;
  input           drp_sel;
  input           drp_wr;
  input   [11:0]  drp_addr;
  input   [15:0]  drp_wdata;
  output  [15:0]  drp_rdata;
  output          drp_ready;
  output          drp_locked;

  // internal signals

  wire            clk_in_s;

  // instantiations

  IBUFGDS i_clk_in_ibuf (
    .I (clk_in_p),
    .IB (clk_in_n),
    .O (clk_in_s));

  generate
  if (MMCM == 1) begin
  ad_mmcm_drp #(
    .MMCM_DEVICE_TYPE (MMCM_DEVICE_TYPE),
    .MMCM_CLKIN_PERIOD  (MMCM_CLKIN_PERIOD),
    .MMCM_VCO_DIV  (MMCM_VCO_DIV),
    .MMCM_VCO_MUL (MMCM_VCO_MUL),
    .MMCM_CLK0_DIV (MMCM_CLK0_DIV),
    .MMCM_CLK1_DIV (MMCM_CLK1_DIV))
  i_mmcm_drp (
    .clk (clk_in_s),
    .mmcm_rst (mmcm_rst),
    .mmcm_clk_0 (clk),
    .mmcm_clk_1 (div_clk),
    .drp_clk (drp_clk),
    .drp_rst (drp_rst),
    .drp_sel (drp_sel),
    .drp_wr (drp_wr),
    .drp_addr (drp_addr),
    .drp_wdata (drp_wdata),
    .drp_rdata (drp_rdata),
    .drp_ready (drp_ready),
    .drp_locked (drp_locked));
  end

  if ((MMCM == 0) && (SERDES == 0)) begin
  BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_buf (
    .CLR (1'b0),
    .CE (1'b1),
    .I (clk_in_s),
    .O (clk));

  assign div_clk = clk;
  end

  if ((MMCM == 0) && (SERDES == 1)) begin
  BUFIO i_clk_buf (
    .I (clk_in_s),
    .O (clk));

  BUFR #(.BUFR_DIVIDE("4")) i_div_clk_buf (
    .CLR (1'b0),
    .CE (1'b1),
    .I (clk_in_s),
    .O (div_clk));
  end
  endgenerate

endmodule

// ***************************************************************************
// ***************************************************************************