#################################################################################### #################################################################################### ## Copyright 2011(c) Analog Devices, Inc. ## Auto-generated, do not modify! #################################################################################### #################################################################################### ifeq ($(MMU),) MMU := 1 endif export ALT_NIOS_MMU_ENABLED := $(MMU) M_DEPS += system_top.v M_DEPS += system_project.tcl M_DEPS += system_constr.sdc M_DEPS += system_bd.qsys M_DEPS += ../common/arradio_bd.qsys M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../common/c5soc/c5soc_system_bd.qsys M_DEPS += ../../common/c5soc/c5soc_system_assign.tcl M_DEPS += ../../../altera/axi_ad9361_cmos_if.v M_DEPS += ../../../altera/axi_ad9361_lvds_if.v M_DEPS += ../../../library/altera/common/ad_cmos_clk.v M_DEPS += ../../../library/altera/common/ad_cmos_in.v M_DEPS += ../../../library/altera/common/ad_cmos_out.v M_DEPS += ../../../library/altera/common/ad_dcfilter.v M_DEPS += ../../../library/altera/common/ad_lvds_clk.v M_DEPS += ../../../library/altera/common/ad_lvds_in.v M_DEPS += ../../../library/altera/common/ad_lvds_out.v M_DEPS += ../../../library/altera/common/ad_mul.v M_DEPS += ../../../library/altera/common/ad_serdes_clk.v M_DEPS += ../../../library/altera/common/ad_serdes_in.v M_DEPS += ../../../library/altera/common/ad_serdes_out.v M_DEPS += ../../../library/axi_ad9361/axi_ad9361.v M_DEPS += ../../../library/axi_ad9361/axi_ad9361_hw.tcl M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx.v M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_channel.v M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_pnmon.v M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd.v M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd_if.v M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx.v M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx_channel.v M_DEPS += ../../../library/axi_dmac/2d_transfer.v M_DEPS += ../../../library/axi_dmac/address_generator.v M_DEPS += ../../../library/axi_dmac/axi_dmac.v M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl M_DEPS += ../../../library/axi_dmac/axi_register_slice.v M_DEPS += ../../../library/axi_dmac/data_mover.v M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v M_DEPS += ../../../library/axi_dmac/inc_id.h M_DEPS += ../../../library/axi_dmac/request_arb.v M_DEPS += ../../../library/axi_dmac/request_generator.v M_DEPS += ../../../library/axi_dmac/resp.h M_DEPS += ../../../library/axi_dmac/response_generator.v M_DEPS += ../../../library/axi_dmac/response_handler.v M_DEPS += ../../../library/axi_dmac/splitter.v M_DEPS += ../../../library/axi_dmac/src_axi_mm.v M_DEPS += ../../../library/axi_dmac/src_axi_stream.v M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v M_DEPS += ../../../library/common/ad_addsub.v M_DEPS += ../../../library/common/ad_datafmt.v M_DEPS += ../../../library/common/ad_dds.v M_DEPS += ../../../library/common/ad_dds_1.v M_DEPS += ../../../library/common/ad_dds_sine.v M_DEPS += ../../../library/common/ad_iqcor.v M_DEPS += ../../../library/common/ad_mem.v M_DEPS += ../../../library/common/ad_pnmon.v M_DEPS += ../../../library/common/ad_rst.v M_DEPS += ../../../library/common/ad_tdd_control.v M_DEPS += ../../../library/common/sync_bits.v M_DEPS += ../../../library/common/sync_gray.v M_DEPS += ../../../library/common/up_adc_channel.v M_DEPS += ../../../library/common/up_adc_common.v M_DEPS += ../../../library/common/up_axi.v M_DEPS += ../../../library/common/up_clock_mon.v M_DEPS += ../../../library/common/up_dac_channel.v M_DEPS += ../../../library/common/up_dac_common.v M_DEPS += ../../../library/common/up_delay_cntrl.v M_DEPS += ../../../library/common/up_tdd_cntrl.v M_DEPS += ../../../library/common/up_xfer_cntrl.v M_DEPS += ../../../library/common/up_xfer_status.v M_DEPS += ../../../library/util_axis_fifo/address_gray.v M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v M_DEPS += ../../../library/util_axis_fifo/address_sync.v M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v M_DEPS += ../../../library/util_cpack/util_cpack.v M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl M_DEPS += ../../../library/util_cpack/util_cpack_mux.v M_DEPS += ../../../library/util_rfifo/util_rfifo.v M_DEPS += ../../../library/util_rfifo/util_rfifo_hw.tcl M_DEPS += ../../../library/util_upack/util_upack.v M_DEPS += ../../../library/util_upack/util_upack_dmx.v M_DEPS += ../../../library/util_upack/util_upack_dsf.v M_DEPS += ../../../library/util_upack/util_upack_hw.tcl M_DEPS += ../../../library/util_wfifo/util_wfifo.v M_DEPS += ../../../library/util_wfifo/util_wfifo_hw.tcl M_ALTERA := quartus_sh --64bit -t M_FLIST += *.log M_FLIST += *_INFO.txt M_FLIST += *_dump.txt M_FLIST += db M_FLIST += *.asm.rpt M_FLIST += *.done M_FLIST += *.eda.rpt M_FLIST += *.fit.* M_FLIST += *.map.* M_FLIST += *.sta.* M_FLIST += *.qsf M_FLIST += *.qpf M_FLIST += *.qws M_FLIST += *.sof M_FLIST += *.cdf M_FLIST += *.sld M_FLIST += *.qdf M_FLIST += hc_output M_FLIST += system_bd M_FLIST += hps_isw_handoff M_FLIST += hps_sdram_*.csv M_FLIST += *ddr3_*.csv M_FLIST += incremental_db M_FLIST += reconfig_mif M_FLIST += *.sopcinfo M_FLIST += *.jdi M_FLIST += *.pin M_FLIST += *_summary.csv M_FLIST += *.dpf .PHONY: all clean clean-all all: arradio_c5soc.sof clean:clean-all clean-all: rm -rf $(M_FLIST) arradio_c5soc.sof: $(M_DEPS) -rm -rf $(M_FLIST) $(M_ALTERA) system_project.tcl >> arradio_c5soc_quartus.log 2>&1 #################################################################################### ####################################################################################