// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
// 
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// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************

`timescale 1ns/100ps

module ad_dds_1 (

  // interface

  clk,
  sclr,
  phase_in,
  sine);

  // interface

  input           clk;
  input           sclr;
  input   [15:0]  phase_in;
  output  [15:0]  sine;

  // xilinx dds ip

  ad_dds_1_xip i_dds_1_xip (
    .aclk (clk),
    .aresetn (~sclr),
    .s_axis_phase_tvalid (1'b1),
    .s_axis_phase_tdata (phase_in),
    .m_axis_data_tvalid (),
    .m_axis_data_tdata (sine));
  
endmodule

// ***************************************************************************
// ***************************************************************************