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// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//  Author: Lars-Peter Clausen <lars@metafoo.de>
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/*
 * Helper module for synchronizing bit signals from one clock domain to another.
 * It uses the standard approach of 2 FF in series.
 * Note, that while the module allows to synchronize multiple bits at once it is
 * only able to synchronize multi-bit signals where at max one bit changes per
 * clock cycle (e.g. a gray counter).
 */
module sync_bits
(
	input [NUM_BITS-1:0] in,
	input out_resetn,
	input out_clk,
	output [NUM_BITS-1:0] out
);

// Number of bits to synchronize
parameter NUM_BITS = 1;
// Whether input and output clocks are asynchronous, if 0 the synchronizer will
// be bypassed and the output signal equals the input signal.
parameter CLK_ASYNC = 1;

reg [NUM_BITS-1:0] cdc_sync_stage1 = 'h0;
reg [NUM_BITS-1:0] cdc_sync_stage2 = 'h0;

always @(posedge out_clk)
begin
	if (out_resetn == 1'b0) begin
		cdc_sync_stage1 <= 'b0;
		cdc_sync_stage2 <= 'b0;
	end else begin
		cdc_sync_stage1 <= in;
		cdc_sync_stage2 <= cdc_sync_stage1;
	end
end

assign out = CLK_ASYNC ? cdc_sync_stage2 : in;

endmodule