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`timescale 1ns/1ns

module prcfg_dac(

  clk,

  // control ports
  control,
  status,

  // FIFO interface
  src_dac_en,
  src_dac_ddata,
  src_dac_dunf,
  src_dac_dvalid,

  dst_dac_en,
  dst_dac_ddata,
  dst_dac_dunf,
  dst_dac_dvalid
);

  parameter   CHANNEL_ID    = 0;
  parameter   DATA_WIDTH    = 32;

  localparam  SYMBOL_WIDTH  = 2;
  localparam  RP_ID         = 8'hA2;

  input                               clk;

  input   [31:0]                      control;
  output  [31:0]                      status;

  output                              src_dac_en;
  input   [(DATA_WIDTH-1):0]          src_dac_ddata;
  input                               src_dac_dunf;
  input                               src_dac_dvalid;

  input                               dst_dac_en;
  output  [(DATA_WIDTH-1):0]          dst_dac_ddata;
  output                              dst_dac_dunf;
  output                              dst_dac_dvalid;

  // output register to improve timing
  reg                                 dst_dac_dunf   = 'h0;
  reg     [(DATA_WIDTH-1):0]          dst_dac_ddata  = 'h0;
  reg                                 dst_dac_dvalid = 'h0;
  reg                                 src_dac_en     = 'h0;

  // internal registers
  reg     [ 7:0]                      pn_data        = 'hF2;
  reg     [31:0]                      status         = 'h0;
  reg     [ 3:0]                      mode           = 'h0;

  // internal wires
  wire    [(SYMBOL_WIDTH-1):0]        mod_data;
  wire    [15:0]                      dac_data_fltr_i;
  wire    [15:0]                      dac_data_fltr_q;

  // prbs function
  function [ 7:0] pn;
    input [ 7:0] din;
    reg   [ 7:0] dout;
    begin
      dout[7] = din[6];
      dout[6] = din[5];
      dout[5] = din[4];
      dout[4] = din[3];
      dout[3] = din[2];
      dout[2] = din[1];
      dout[1] = din[7] ^ din[4];
      dout[0] = din[6] ^ din[3];
      pn = dout;
    end
  endfunction

  // update control and status registers
  always @(posedge clk) begin
    status <= { 24'h0, RP_ID };
    mode   <= control[ 7:4];
  end

  // prbs generation
  always @(posedge clk) begin
    if(dst_dac_en == 1) begin
      pn_data <= pn(pn_data);
    end
  end

  // data for the modulator (prbs or dma)
  assign mod_data = (mode == 1) ? pn_data[ 1:0] : src_dac_ddata[ 1:0];

  // qpsk modulator
  qpsk_mod i_qpsk_mod (
    .clk(clk),
    .data_input(mod_data),
    .data_valid(dst_dac_en),
    .data_qpsk_i(dac_data_fltr_i),
    .data_qpsk_q(dac_data_fltr_q)
  );

  // output logic
  always @(posedge clk) begin

    src_dac_en     <= dst_dac_en;
    dst_dac_dvalid <= src_dac_dvalid;

    case(mode)
      4'h0 : begin
        dst_dac_ddata <= src_dac_ddata;
        dst_dac_dunf  <= src_dac_dunf;
      end
      4'h1 : begin
        dst_dac_ddata <= { dac_data_fltr_q, dac_data_fltr_i };
        dst_dac_dunf  <= 1'h0;
      end
      4'h2 : begin
        dst_dac_ddata <= { dac_data_fltr_q, dac_data_fltr_i };
        dst_dac_dunf  <= src_dac_dunf;
      end
      default : begin
      end
    endcase

  end
endmodule