// ***************************************************************************
// ***************************************************************************
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// ***************************************************************************
// ***************************************************************************

`timescale 1ns/100ps

module util_var_fifo #(

  parameter       DATA_WIDTH = 32,
  parameter       ADDRESS_WIDTH =  13) (

  input                   clk,
  input                   rst,

  input       [31:0]      depth,

  input       [ -1:0]     data_in,
  input                   data_in_valid,

  output      [DATA_WIDTH-1:0]  data_out,
  output                  data_out_valid
);


  localparam      MAX_DEPTH = (2 ** ADDRESS_WIDTH) - 1;

  // internal registers

  reg     [ADDRESS_WIDTH-1:0]    addra = 'd0;
  reg     [ADDRESS_WIDTH-1:0]    addrb = 'd0;

  reg     [31:0]    depth_d1 = 'd0;
  reg     [31:0]    data_in_d1 = 'd0;
  reg     [31:0]    data_in_d2 = 'd0;
  reg               data_active = 'd0;

  // internal signals

  wire                    reset;
  wire  [31:0]            depth;
  wire  [DATA_WIDTH-1:0]  data_out_s;
  wire                    data_out_valid_s;

  assign reset = ((rst == 1'b1) || (depth != depth_d1)) ? 1 : 0;

  assign data_out = (depth == 0) ? data_in_d2 : data_out_s;
  assign data_out_valid_s = data_active & data_in_valid;
  assign data_out_valid = (depth == 0) ? data_in_valid : data_out_valid_s;

  always @(posedge clk) begin
    depth_d1 <= depth;
    data_in_d1 <= data_in;
    data_in_d2 <= data_in_d1;
  end

  always @(posedge clk) begin
    if(reset == 1'b1) begin
      addra <= 0;
      addrb <= 0;
      data_active <= 1'b0;
    end else begin
      if (data_in_valid == 1'b1) begin
        addra <= addra + 1;
        if (data_active == 1'b1) begin
          addrb <= addrb + 1;
        end
      end
      if (addra >= depth || addra > MAX_DEPTH - 2) begin
        data_active <= 1'b1;
      end
    end
  end

  ad_mem #(
    .DATA_WIDTH(DATA_WIDTH),
    .ADDRESS_WIDTH(ADDRESS_WIDTH)
  ) data_fifo (
    .clka(clk),
    .wea(data_in_valid),
    .addra(addra),
    .dina(data_in),

    .clkb(clk),
    .addrb(addrb),
    .doutb(data_out_s));

endmodule

// ***************************************************************************
// ***************************************************************************