####################################################################################
## Copyright (c) 2018 - 2021 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################

LIBRARY_NAME := axi_ad9152

GENERIC_DEPS += axi_ad9152.v

XILINX_DEPS += axi_ad9152_ip.tcl

XILINX_LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac

INTEL_DEPS += ../common/ad_dds.v
INTEL_DEPS += ../common/ad_dds_1.v
INTEL_DEPS += ../common/ad_dds_2.v
INTEL_DEPS += ../common/ad_dds_cordic_pipe.v
INTEL_DEPS += ../common/ad_dds_sine.v
INTEL_DEPS += ../common/ad_dds_sine_cordic.v
INTEL_DEPS += ../common/ad_iqcor.v
INTEL_DEPS += ../common/ad_perfect_shuffle.v
INTEL_DEPS += ../common/ad_rst.v
INTEL_DEPS += ../common/up_axi.v
INTEL_DEPS += ../common/up_clock_mon.v
INTEL_DEPS += ../common/up_dac_channel.v
INTEL_DEPS += ../common/up_dac_common.v
INTEL_DEPS += ../common/up_xfer_cntrl.v
INTEL_DEPS += ../common/up_xfer_status.v
INTEL_DEPS += ../intel/common/ad_mul.v
INTEL_DEPS += ../intel/common/up_clock_mon_constr.sdc
INTEL_DEPS += ../intel/common/up_rst_constr.sdc
INTEL_DEPS += ../intel/common/up_xfer_cntrl_constr.sdc
INTEL_DEPS += ../intel/common/up_xfer_status_constr.sdc
INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v
INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v
INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v
INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v
INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v
INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_pn.v
INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v
INTEL_DEPS += axi_ad9152_hw.tcl

include ../scripts/library.mk