// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
// 
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// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************

`timescale 1ns/100ps

module util_rfifo (

  rstn,

  m_clk,
  m_rd,
  m_rdata,
  m_runf,
  s_clk,
  s_rd,
  s_rdata,
  s_runf,

  fifo_rst,
  fifo_wr,
  fifo_wdata,
  fifo_wfull,
  fifo_rd,
  fifo_rdata,
  fifo_rempty,
  fifo_runf);

  // parameters (S) bus width must be greater than (M)

  parameter M_DATA_WIDTH = 32;
  parameter S_DATA_WIDTH = 64;
 
  // common clock

  input                           rstn;

  // master/slave write 

  input                           m_clk;
  input                           m_rd;
  output  [M_DATA_WIDTH-1:0]      m_rdata;
  output                          m_runf;
  input                           s_clk;
  output                          s_rd;
  input   [S_DATA_WIDTH-1:0]      s_rdata;
  input                           s_runf;

  // fifo interface

  output                          fifo_rst;
  output                          fifo_wr;
  output  [S_DATA_WIDTH-1:0]      fifo_wdata;
  input                           fifo_wfull;
  output                          fifo_rd;
  input   [M_DATA_WIDTH-1:0]      fifo_rdata;
  input                           fifo_rempty;
  input                           fifo_runf;

  // internal registers

  reg                             s_rd = 'd0;
  reg                             fifo_wr = 'd0;
  reg                             m_runf_m1 = 'd0;
  reg                             m_runf_m2 = 'd0;
  reg                             m_runf = 'd0;

  // internal signals

  wire                            m_runf_s;

  // defaults

  assign fifo_rst = ~rstn;

  // independent clocks and buswidths- simply expect
  // user to set a reasonable threshold on the full signal

  always @(posedge s_clk) begin
    s_rd <= ~fifo_wfull;
    fifo_wr <= ~fifo_wfull;
  end

  genvar s;
  generate
  for (s = 0; s < S_DATA_WIDTH; s = s + 1) begin: g_wdata
  assign fifo_wdata[s] = s_rdata[(S_DATA_WIDTH-1)-s];
  end
  endgenerate

  // read is non-destructive

  assign fifo_rd = m_rd;
  assign m_runf_s = s_runf | fifo_runf;

  always @(posedge m_clk) begin
    m_runf_m1 <= m_runf_s;
    m_runf_m2 <= m_runf_m1;
    m_runf <= m_runf_m2;
  end
  
  genvar m;
  generate
  for (m = 0; m < M_DATA_WIDTH; m = m + 1) begin: g_rdata
  assign m_rdata[m] = fifo_rdata[(M_DATA_WIDTH-1)-m];
  end
  endgenerate

endmodule

// ***************************************************************************
// ***************************************************************************