####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################

LIBRARY_NAME := axi_ad9152

GENERIC_DEPS += axi_ad9152.v

XILINX_DEPS += axi_ad9152_ip.tcl

XILINX_LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac

ALTERA_DEPS += ../altera/common/ad_mul.v
ALTERA_DEPS += ../altera/common/up_clock_mon_constr.sdc
ALTERA_DEPS += ../altera/common/up_rst_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_cntrl_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_status_constr.sdc
ALTERA_DEPS += ../common/ad_dds.v
ALTERA_DEPS += ../common/ad_dds_1.v
ALTERA_DEPS += ../common/ad_dds_sine.v
ALTERA_DEPS += ../common/ad_rst.v
ALTERA_DEPS += ../common/up_axi.v
ALTERA_DEPS += ../common/up_clock_mon.v
ALTERA_DEPS += ../common/up_dac_channel.v
ALTERA_DEPS += ../common/up_dac_common.v
ALTERA_DEPS += ../common/up_xfer_cntrl.v
ALTERA_DEPS += ../common/up_xfer_status.v
ALTERA_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v
ALTERA_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v
ALTERA_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v
ALTERA_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v
ALTERA_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v
ALTERA_DEPS += axi_ad9152_hw.tcl

include ../scripts/library.mk