// -----------------------------------------------------------------------------
//
// Copyright 2013(c) Analog Devices, Inc.
//
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// -----------------------------------------------------------------------------
// FILE NAME : debouncer.v
// MODULE NAME : debouncer
// AUTHOR : ACozma
// AUTHOR'S EMAIL : andrei.cozma@analog.com
// -----------------------------------------------------------------------------
// KEYWORDS :
// -----------------------------------------------------------------------------
// PURPOSE : Module used for debouncing input signals
// -----------------------------------------------------------------------------
// REUSE ISSUES
// Reset Strategy      :
// Clock Domains       :
// Critical Timing     :
// Test Features       :
// Asynchronous I/F    :
// Instantiations      :
// Synthesizable (y/n) : y
// Target Device       :
// Other               :
// -----------------------------------------------------------------------------

`timescale 1ns / 1ps

module debouncer
//----------- Paramters Declarations -------------------------------------------
#(
    parameter DEBOUNCER_LENGTH = 4
)
//----------- Ports Declarations -----------------------------------------------
(
    input       clk_i,
    input       rst_i,
    input       sig_i,
    output reg  sig_o
);
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
reg [DEBOUNCER_LENGTH-1:0] shift_reg;

//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------

always @(posedge clk_i)
begin
    if(rst_i == 1)
    begin
        shift_reg   <= 0;
        sig_o       <= 0;
    end
    else
    begin
        shift_reg <= {shift_reg[DEBOUNCER_LENGTH-2:0], sig_i};
        if(shift_reg == {DEBOUNCER_LENGTH{1'b1}})
        begin
            sig_o <= 1'b1;
        end
        else if(shift_reg == {DEBOUNCER_LENGTH{1'b0}})
        begin
            sig_o <= 1'b0;
        end
    end
end

endmodule