// *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. // // All rights reserved. // // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // - Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in // the documentation and/or other materials provided with the // distribution. // - Neither the name of Analog Devices, Inc. nor the names of its // contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // - The use of this software may or may not infringe the patent rights // of one or more patent holders. This license does not release you // from the requirement that you obtain separate licenses from these // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. // // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY // RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** `timescale 1ns/1ps module util_adxcvr ( input up_rstn, input up_clk, input qpll_ref_clk_00, input cpll_ref_clk_00, input rx_00_p, input rx_00_n, output rx_out_clk_00, input rx_clk_00, output [ 3:0] rx_charisk_00, output [ 3:0] rx_disperr_00, output [ 3:0] rx_notintable_00, output [31:0] rx_data_00, input rx_calign_00, output tx_00_p, output tx_00_n, output tx_out_clk_00, input tx_clk_00, input [ 3:0] tx_charisk_00, input [31:0] tx_data_00, input [ 7:0] up_cm_sel_00, input up_cm_enb_00, input [11:0] up_cm_addr_00, input up_cm_wr_00, input [15:0] up_cm_wdata_00, output [15:0] up_cm_rdata_00, output up_cm_ready_00, input [ 7:0] up_es_sel_00, input up_es_enb_00, input [11:0] up_es_addr_00, input up_es_wr_00, input [15:0] up_es_wdata_00, output [15:0] up_es_rdata_00, output up_es_ready_00, input up_rx_pll_rst_00, output up_rx_pll_locked_00, input up_rx_rst_00, input up_rx_user_ready_00, output up_rx_rst_done_00, input up_rx_lpm_dfe_n_00, input [ 2:0] up_rx_rate_00, input [ 1:0] up_rx_sys_clk_sel_00, input [ 2:0] up_rx_out_clk_sel_00, input [ 7:0] up_rx_sel_00, input up_rx_enb_00, input [11:0] up_rx_addr_00, input up_rx_wr_00, input [15:0] up_rx_wdata_00, output [15:0] up_rx_rdata_00, output up_rx_ready_00, input up_tx_pll_rst_00, output up_tx_pll_locked_00, input up_tx_rst_00, input up_tx_user_ready_00, output up_tx_rst_done_00, input up_tx_lpm_dfe_n_00, input [ 2:0] up_tx_rate_00, input [ 1:0] up_tx_sys_clk_sel_00, input [ 2:0] up_tx_out_clk_sel_00, input [ 7:0] up_tx_sel_00, input up_tx_enb_00, input [11:0] up_tx_addr_00, input up_tx_wr_00, input [15:0] up_tx_wdata_00, output [15:0] up_tx_rdata_00, output up_tx_ready_00, input cpll_ref_clk_01, input rx_01_p, input rx_01_n, output rx_out_clk_01, input rx_clk_01, output [ 3:0] rx_charisk_01, output [ 3:0] rx_disperr_01, output [ 3:0] rx_notintable_01, output [31:0] rx_data_01, input rx_calign_01, output tx_01_p, output tx_01_n, output tx_out_clk_01, input tx_clk_01, input [ 3:0] tx_charisk_01, input [31:0] tx_data_01, input [ 7:0] up_es_sel_01, input up_es_enb_01, input [11:0] up_es_addr_01, input up_es_wr_01, input [15:0] up_es_wdata_01, output [15:0] up_es_rdata_01, output up_es_ready_01, input up_rx_pll_rst_01, output up_rx_pll_locked_01, input up_rx_rst_01, input up_rx_user_ready_01, output up_rx_rst_done_01, input up_rx_lpm_dfe_n_01, input [ 2:0] up_rx_rate_01, input [ 1:0] up_rx_sys_clk_sel_01, input [ 2:0] up_rx_out_clk_sel_01, input [ 7:0] up_rx_sel_01, input up_rx_enb_01, input [11:0] up_rx_addr_01, input up_rx_wr_01, input [15:0] up_rx_wdata_01, output [15:0] up_rx_rdata_01, output up_rx_ready_01, input up_tx_pll_rst_01, output up_tx_pll_locked_01, input up_tx_rst_01, input up_tx_user_ready_01, output up_tx_rst_done_01, input up_tx_lpm_dfe_n_01, input [ 2:0] up_tx_rate_01, input [ 1:0] up_tx_sys_clk_sel_01, input [ 2:0] up_tx_out_clk_sel_01, input [ 7:0] up_tx_sel_01, input up_tx_enb_01, input [11:0] up_tx_addr_01, input up_tx_wr_01, input [15:0] up_tx_wdata_01, output [15:0] up_tx_rdata_01, output up_tx_ready_01, input cpll_ref_clk_02, input rx_02_p, input rx_02_n, output rx_out_clk_02, input rx_clk_02, output [ 3:0] rx_charisk_02, output [ 3:0] rx_disperr_02, output [ 3:0] rx_notintable_02, output [31:0] rx_data_02, input rx_calign_02, output tx_02_p, output tx_02_n, output tx_out_clk_02, input tx_clk_02, input [ 3:0] tx_charisk_02, input [31:0] tx_data_02, input [ 7:0] up_es_sel_02, input up_es_enb_02, input [11:0] up_es_addr_02, input up_es_wr_02, input [15:0] up_es_wdata_02, output [15:0] up_es_rdata_02, output up_es_ready_02, input up_rx_pll_rst_02, output up_rx_pll_locked_02, input up_rx_rst_02, input up_rx_user_ready_02, output up_rx_rst_done_02, input up_rx_lpm_dfe_n_02, input [ 2:0] up_rx_rate_02, input [ 1:0] up_rx_sys_clk_sel_02, input [ 2:0] up_rx_out_clk_sel_02, input [ 7:0] up_rx_sel_02, input up_rx_enb_02, input [11:0] up_rx_addr_02, input up_rx_wr_02, input [15:0] up_rx_wdata_02, output [15:0] up_rx_rdata_02, output up_rx_ready_02, input up_tx_pll_rst_02, output up_tx_pll_locked_02, input up_tx_rst_02, input up_tx_user_ready_02, output up_tx_rst_done_02, input up_tx_lpm_dfe_n_02, input [ 2:0] up_tx_rate_02, input [ 1:0] up_tx_sys_clk_sel_02, input [ 2:0] up_tx_out_clk_sel_02, input [ 7:0] up_tx_sel_02, input up_tx_enb_02, input [11:0] up_tx_addr_02, input up_tx_wr_02, input [15:0] up_tx_wdata_02, output [15:0] up_tx_rdata_02, output up_tx_ready_02, input cpll_ref_clk_03, input rx_03_p, input rx_03_n, output rx_out_clk_03, input rx_clk_03, output [ 3:0] rx_charisk_03, output [ 3:0] rx_disperr_03, output [ 3:0] rx_notintable_03, output [31:0] rx_data_03, input rx_calign_03, output tx_03_p, output tx_03_n, output tx_out_clk_03, input tx_clk_03, input [ 3:0] tx_charisk_03, input [31:0] tx_data_03, input [ 7:0] up_es_sel_03, input up_es_enb_03, input [11:0] up_es_addr_03, input up_es_wr_03, input [15:0] up_es_wdata_03, output [15:0] up_es_rdata_03, output up_es_ready_03, input up_rx_pll_rst_03, output up_rx_pll_locked_03, input up_rx_rst_03, input up_rx_user_ready_03, output up_rx_rst_done_03, input up_rx_lpm_dfe_n_03, input [ 2:0] up_rx_rate_03, input [ 1:0] up_rx_sys_clk_sel_03, input [ 2:0] up_rx_out_clk_sel_03, input [ 7:0] up_rx_sel_03, input up_rx_enb_03, input [11:0] up_rx_addr_03, input up_rx_wr_03, input [15:0] up_rx_wdata_03, output [15:0] up_rx_rdata_03, output up_rx_ready_03, input up_tx_pll_rst_03, output up_tx_pll_locked_03, input up_tx_rst_03, input up_tx_user_ready_03, output up_tx_rst_done_03, input up_tx_lpm_dfe_n_03, input [ 2:0] up_tx_rate_03, input [ 1:0] up_tx_sys_clk_sel_03, input [ 2:0] up_tx_out_clk_sel_03, input [ 7:0] up_tx_sel_03, input up_tx_enb_03, input [11:0] up_tx_addr_03, input up_tx_wr_03, input [15:0] up_tx_wdata_03, output [15:0] up_tx_rdata_03, output up_tx_ready_03, input qpll_ref_clk_04, input cpll_ref_clk_04, input rx_04_p, input rx_04_n, output rx_out_clk_04, input rx_clk_04, output [ 3:0] rx_charisk_04, output [ 3:0] rx_disperr_04, output [ 3:0] rx_notintable_04, output [31:0] rx_data_04, input rx_calign_04, output tx_04_p, output tx_04_n, output tx_out_clk_04, input tx_clk_04, input [ 3:0] tx_charisk_04, input [31:0] tx_data_04, input [ 7:0] up_cm_sel_04, input up_cm_enb_04, input [11:0] up_cm_addr_04, input up_cm_wr_04, input [15:0] up_cm_wdata_04, output [15:0] up_cm_rdata_04, output up_cm_ready_04, input [ 7:0] up_es_sel_04, input up_es_enb_04, input [11:0] up_es_addr_04, input up_es_wr_04, input [15:0] up_es_wdata_04, output [15:0] up_es_rdata_04, output up_es_ready_04, input up_rx_pll_rst_04, output up_rx_pll_locked_04, input up_rx_rst_04, input up_rx_user_ready_04, output up_rx_rst_done_04, input up_rx_lpm_dfe_n_04, input [ 2:0] up_rx_rate_04, input [ 1:0] up_rx_sys_clk_sel_04, input [ 2:0] up_rx_out_clk_sel_04, input [ 7:0] up_rx_sel_04, input up_rx_enb_04, input [11:0] up_rx_addr_04, input up_rx_wr_04, input [15:0] up_rx_wdata_04, output [15:0] up_rx_rdata_04, output up_rx_ready_04, input up_tx_pll_rst_04, output up_tx_pll_locked_04, input up_tx_rst_04, input up_tx_user_ready_04, output up_tx_rst_done_04, input up_tx_lpm_dfe_n_04, input [ 2:0] up_tx_rate_04, input [ 1:0] up_tx_sys_clk_sel_04, input [ 2:0] up_tx_out_clk_sel_04, input [ 7:0] up_tx_sel_04, input up_tx_enb_04, input [11:0] up_tx_addr_04, input up_tx_wr_04, input [15:0] up_tx_wdata_04, output [15:0] up_tx_rdata_04, output up_tx_ready_04, input cpll_ref_clk_05, input rx_05_p, input rx_05_n, output rx_out_clk_05, input rx_clk_05, output [ 3:0] rx_charisk_05, output [ 3:0] rx_disperr_05, output [ 3:0] rx_notintable_05, output [31:0] rx_data_05, input rx_calign_05, output tx_05_p, output tx_05_n, output tx_out_clk_05, input tx_clk_05, input [ 3:0] tx_charisk_05, input [31:0] tx_data_05, input [ 7:0] up_es_sel_05, input up_es_enb_05, input [11:0] up_es_addr_05, input up_es_wr_05, input [15:0] up_es_wdata_05, output [15:0] up_es_rdata_05, output up_es_ready_05, input up_rx_pll_rst_05, output up_rx_pll_locked_05, input up_rx_rst_05, input up_rx_user_ready_05, output up_rx_rst_done_05, input up_rx_lpm_dfe_n_05, input [ 2:0] up_rx_rate_05, input [ 1:0] up_rx_sys_clk_sel_05, input [ 2:0] up_rx_out_clk_sel_05, input [ 7:0] up_rx_sel_05, input up_rx_enb_05, input [11:0] up_rx_addr_05, input up_rx_wr_05, input [15:0] up_rx_wdata_05, output [15:0] up_rx_rdata_05, output up_rx_ready_05, input up_tx_pll_rst_05, output up_tx_pll_locked_05, input up_tx_rst_05, input up_tx_user_ready_05, output up_tx_rst_done_05, input up_tx_lpm_dfe_n_05, input [ 2:0] up_tx_rate_05, input [ 1:0] up_tx_sys_clk_sel_05, input [ 2:0] up_tx_out_clk_sel_05, input [ 7:0] up_tx_sel_05, input up_tx_enb_05, input [11:0] up_tx_addr_05, input up_tx_wr_05, input [15:0] up_tx_wdata_05, output [15:0] up_tx_rdata_05, output up_tx_ready_05, input cpll_ref_clk_06, input rx_06_p, input rx_06_n, output rx_out_clk_06, input rx_clk_06, output [ 3:0] rx_charisk_06, output [ 3:0] rx_disperr_06, output [ 3:0] rx_notintable_06, output [31:0] rx_data_06, input rx_calign_06, output tx_06_p, output tx_06_n, output tx_out_clk_06, input tx_clk_06, input [ 3:0] tx_charisk_06, input [31:0] tx_data_06, input [ 7:0] up_es_sel_06, input up_es_enb_06, input [11:0] up_es_addr_06, input up_es_wr_06, input [15:0] up_es_wdata_06, output [15:0] up_es_rdata_06, output up_es_ready_06, input up_rx_pll_rst_06, output up_rx_pll_locked_06, input up_rx_rst_06, input up_rx_user_ready_06, output up_rx_rst_done_06, input up_rx_lpm_dfe_n_06, input [ 2:0] up_rx_rate_06, input [ 1:0] up_rx_sys_clk_sel_06, input [ 2:0] up_rx_out_clk_sel_06, input [ 7:0] up_rx_sel_06, input up_rx_enb_06, input [11:0] up_rx_addr_06, input up_rx_wr_06, input [15:0] up_rx_wdata_06, output [15:0] up_rx_rdata_06, output up_rx_ready_06, input up_tx_pll_rst_06, output up_tx_pll_locked_06, input up_tx_rst_06, input up_tx_user_ready_06, output up_tx_rst_done_06, input up_tx_lpm_dfe_n_06, input [ 2:0] up_tx_rate_06, input [ 1:0] up_tx_sys_clk_sel_06, input [ 2:0] up_tx_out_clk_sel_06, input [ 7:0] up_tx_sel_06, input up_tx_enb_06, input [11:0] up_tx_addr_06, input up_tx_wr_06, input [15:0] up_tx_wdata_06, output [15:0] up_tx_rdata_06, output up_tx_ready_06, input cpll_ref_clk_07, input rx_07_p, input rx_07_n, output rx_out_clk_07, input rx_clk_07, output [ 3:0] rx_charisk_07, output [ 3:0] rx_disperr_07, output [ 3:0] rx_notintable_07, output [31:0] rx_data_07, input rx_calign_07, output tx_07_p, output tx_07_n, output tx_out_clk_07, input tx_clk_07, input [ 3:0] tx_charisk_07, input [31:0] tx_data_07, input [ 7:0] up_es_sel_07, input up_es_enb_07, input [11:0] up_es_addr_07, input up_es_wr_07, input [15:0] up_es_wdata_07, output [15:0] up_es_rdata_07, output up_es_ready_07, input up_rx_pll_rst_07, output up_rx_pll_locked_07, input up_rx_rst_07, input up_rx_user_ready_07, output up_rx_rst_done_07, input up_rx_lpm_dfe_n_07, input [ 2:0] up_rx_rate_07, input [ 1:0] up_rx_sys_clk_sel_07, input [ 2:0] up_rx_out_clk_sel_07, input [ 7:0] up_rx_sel_07, input up_rx_enb_07, input [11:0] up_rx_addr_07, input up_rx_wr_07, input [15:0] up_rx_wdata_07, output [15:0] up_rx_rdata_07, output up_rx_ready_07, input up_tx_pll_rst_07, output up_tx_pll_locked_07, input up_tx_rst_07, input up_tx_user_ready_07, output up_tx_rst_done_07, input up_tx_lpm_dfe_n_07, input [ 2:0] up_tx_rate_07, input [ 1:0] up_tx_sys_clk_sel_07, input [ 2:0] up_tx_out_clk_sel_07, input [ 7:0] up_tx_sel_07, input up_tx_enb_07, input [11:0] up_tx_addr_07, input up_tx_wr_07, input [15:0] up_tx_wdata_07, output [15:0] up_tx_rdata_07, output up_tx_ready_07, input qpll_ref_clk_08, input cpll_ref_clk_08, input rx_08_p, input rx_08_n, output rx_out_clk_08, input rx_clk_08, output [ 3:0] rx_charisk_08, output [ 3:0] rx_disperr_08, output [ 3:0] rx_notintable_08, output [31:0] rx_data_08, input rx_calign_08, output tx_08_p, output tx_08_n, output tx_out_clk_08, input tx_clk_08, input [ 3:0] tx_charisk_08, input [31:0] tx_data_08, input [ 7:0] up_cm_sel_08, input up_cm_enb_08, input [11:0] up_cm_addr_08, input up_cm_wr_08, input [15:0] up_cm_wdata_08, output [15:0] up_cm_rdata_08, output up_cm_ready_08, input [ 7:0] up_es_sel_08, input up_es_enb_08, input [11:0] up_es_addr_08, input up_es_wr_08, input [15:0] up_es_wdata_08, output [15:0] up_es_rdata_08, output up_es_ready_08, input up_rx_pll_rst_08, output up_rx_pll_locked_08, input up_rx_rst_08, input up_rx_user_ready_08, output up_rx_rst_done_08, input up_rx_lpm_dfe_n_08, input [ 2:0] up_rx_rate_08, input [ 1:0] up_rx_sys_clk_sel_08, input [ 2:0] up_rx_out_clk_sel_08, input [ 7:0] up_rx_sel_08, input up_rx_enb_08, input [11:0] up_rx_addr_08, input up_rx_wr_08, input [15:0] up_rx_wdata_08, output [15:0] up_rx_rdata_08, output up_rx_ready_08, input up_tx_pll_rst_08, output up_tx_pll_locked_08, input up_tx_rst_08, input up_tx_user_ready_08, output up_tx_rst_done_08, input up_tx_lpm_dfe_n_08, input [ 2:0] up_tx_rate_08, input [ 1:0] up_tx_sys_clk_sel_08, input [ 2:0] up_tx_out_clk_sel_08, input [ 7:0] up_tx_sel_08, input up_tx_enb_08, input [11:0] up_tx_addr_08, input up_tx_wr_08, input [15:0] up_tx_wdata_08, output [15:0] up_tx_rdata_08, output up_tx_ready_08, input cpll_ref_clk_09, input rx_09_p, input rx_09_n, output rx_out_clk_09, input rx_clk_09, output [ 3:0] rx_charisk_09, output [ 3:0] rx_disperr_09, output [ 3:0] rx_notintable_09, output [31:0] rx_data_09, input rx_calign_09, output tx_09_p, output tx_09_n, output tx_out_clk_09, input tx_clk_09, input [ 3:0] tx_charisk_09, input [31:0] tx_data_09, input [ 7:0] up_es_sel_09, input up_es_enb_09, input [11:0] up_es_addr_09, input up_es_wr_09, input [15:0] up_es_wdata_09, output [15:0] up_es_rdata_09, output up_es_ready_09, input up_rx_pll_rst_09, output up_rx_pll_locked_09, input up_rx_rst_09, input up_rx_user_ready_09, output up_rx_rst_done_09, input up_rx_lpm_dfe_n_09, input [ 2:0] up_rx_rate_09, input [ 1:0] up_rx_sys_clk_sel_09, input [ 2:0] up_rx_out_clk_sel_09, input [ 7:0] up_rx_sel_09, input up_rx_enb_09, input [11:0] up_rx_addr_09, input up_rx_wr_09, input [15:0] up_rx_wdata_09, output [15:0] up_rx_rdata_09, output up_rx_ready_09, input up_tx_pll_rst_09, output up_tx_pll_locked_09, input up_tx_rst_09, input up_tx_user_ready_09, output up_tx_rst_done_09, input up_tx_lpm_dfe_n_09, input [ 2:0] up_tx_rate_09, input [ 1:0] up_tx_sys_clk_sel_09, input [ 2:0] up_tx_out_clk_sel_09, input [ 7:0] up_tx_sel_09, input up_tx_enb_09, input [11:0] up_tx_addr_09, input up_tx_wr_09, input [15:0] up_tx_wdata_09, output [15:0] up_tx_rdata_09, output up_tx_ready_09, input cpll_ref_clk_10, input rx_10_p, input rx_10_n, output rx_out_clk_10, input rx_clk_10, output [ 3:0] rx_charisk_10, output [ 3:0] rx_disperr_10, output [ 3:0] rx_notintable_10, output [31:0] rx_data_10, input rx_calign_10, output tx_10_p, output tx_10_n, output tx_out_clk_10, input tx_clk_10, input [ 3:0] tx_charisk_10, input [31:0] tx_data_10, input [ 7:0] up_es_sel_10, input up_es_enb_10, input [11:0] up_es_addr_10, input up_es_wr_10, input [15:0] up_es_wdata_10, output [15:0] up_es_rdata_10, output up_es_ready_10, input up_rx_pll_rst_10, output up_rx_pll_locked_10, input up_rx_rst_10, input up_rx_user_ready_10, output up_rx_rst_done_10, input up_rx_lpm_dfe_n_10, input [ 2:0] up_rx_rate_10, input [ 1:0] up_rx_sys_clk_sel_10, input [ 2:0] up_rx_out_clk_sel_10, input [ 7:0] up_rx_sel_10, input up_rx_enb_10, input [11:0] up_rx_addr_10, input up_rx_wr_10, input [15:0] up_rx_wdata_10, output [15:0] up_rx_rdata_10, output up_rx_ready_10, input up_tx_pll_rst_10, output up_tx_pll_locked_10, input up_tx_rst_10, input up_tx_user_ready_10, output up_tx_rst_done_10, input up_tx_lpm_dfe_n_10, input [ 2:0] up_tx_rate_10, input [ 1:0] up_tx_sys_clk_sel_10, input [ 2:0] up_tx_out_clk_sel_10, input [ 7:0] up_tx_sel_10, input up_tx_enb_10, input [11:0] up_tx_addr_10, input up_tx_wr_10, input [15:0] up_tx_wdata_10, output [15:0] up_tx_rdata_10, output up_tx_ready_10, input cpll_ref_clk_11, input rx_11_p, input rx_11_n, output rx_out_clk_11, input rx_clk_11, output [ 3:0] rx_charisk_11, output [ 3:0] rx_disperr_11, output [ 3:0] rx_notintable_11, output [31:0] rx_data_11, input rx_calign_11, output tx_11_p, output tx_11_n, output tx_out_clk_11, input tx_clk_11, input [ 3:0] tx_charisk_11, input [31:0] tx_data_11, input [ 7:0] up_es_sel_11, input up_es_enb_11, input [11:0] up_es_addr_11, input up_es_wr_11, input [15:0] up_es_wdata_11, output [15:0] up_es_rdata_11, output up_es_ready_11, input up_rx_pll_rst_11, output up_rx_pll_locked_11, input up_rx_rst_11, input up_rx_user_ready_11, output up_rx_rst_done_11, input up_rx_lpm_dfe_n_11, input [ 2:0] up_rx_rate_11, input [ 1:0] up_rx_sys_clk_sel_11, input [ 2:0] up_rx_out_clk_sel_11, input [ 7:0] up_rx_sel_11, input up_rx_enb_11, input [11:0] up_rx_addr_11, input up_rx_wr_11, input [15:0] up_rx_wdata_11, output [15:0] up_rx_rdata_11, output up_rx_ready_11, input up_tx_pll_rst_11, output up_tx_pll_locked_11, input up_tx_rst_11, input up_tx_user_ready_11, output up_tx_rst_done_11, input up_tx_lpm_dfe_n_11, input [ 2:0] up_tx_rate_11, input [ 1:0] up_tx_sys_clk_sel_11, input [ 2:0] up_tx_out_clk_sel_11, input [ 7:0] up_tx_sel_11, input up_tx_enb_11, input [11:0] up_tx_addr_11, input up_tx_wr_11, input [15:0] up_tx_wdata_11, output [15:0] up_tx_rdata_11, output up_tx_ready_11, input qpll_ref_clk_12, input cpll_ref_clk_12, input rx_12_p, input rx_12_n, output rx_out_clk_12, input rx_clk_12, output [ 3:0] rx_charisk_12, output [ 3:0] rx_disperr_12, output [ 3:0] rx_notintable_12, output [31:0] rx_data_12, input rx_calign_12, output tx_12_p, output tx_12_n, output tx_out_clk_12, input tx_clk_12, input [ 3:0] tx_charisk_12, input [31:0] tx_data_12, input [ 7:0] up_cm_sel_12, input up_cm_enb_12, input [11:0] up_cm_addr_12, input up_cm_wr_12, input [15:0] up_cm_wdata_12, output [15:0] up_cm_rdata_12, output up_cm_ready_12, input [ 7:0] up_es_sel_12, input up_es_enb_12, input [11:0] up_es_addr_12, input up_es_wr_12, input [15:0] up_es_wdata_12, output [15:0] up_es_rdata_12, output up_es_ready_12, input up_rx_pll_rst_12, output up_rx_pll_locked_12, input up_rx_rst_12, input up_rx_user_ready_12, output up_rx_rst_done_12, input up_rx_lpm_dfe_n_12, input [ 2:0] up_rx_rate_12, input [ 1:0] up_rx_sys_clk_sel_12, input [ 2:0] up_rx_out_clk_sel_12, input [ 7:0] up_rx_sel_12, input up_rx_enb_12, input [11:0] up_rx_addr_12, input up_rx_wr_12, input [15:0] up_rx_wdata_12, output [15:0] up_rx_rdata_12, output up_rx_ready_12, input up_tx_pll_rst_12, output up_tx_pll_locked_12, input up_tx_rst_12, input up_tx_user_ready_12, output up_tx_rst_done_12, input up_tx_lpm_dfe_n_12, input [ 2:0] up_tx_rate_12, input [ 1:0] up_tx_sys_clk_sel_12, input [ 2:0] up_tx_out_clk_sel_12, input [ 7:0] up_tx_sel_12, input up_tx_enb_12, input [11:0] up_tx_addr_12, input up_tx_wr_12, input [15:0] up_tx_wdata_12, output [15:0] up_tx_rdata_12, output up_tx_ready_12, input cpll_ref_clk_13, input rx_13_p, input rx_13_n, output rx_out_clk_13, input rx_clk_13, output [ 3:0] rx_charisk_13, output [ 3:0] rx_disperr_13, output [ 3:0] rx_notintable_13, output [31:0] rx_data_13, input rx_calign_13, output tx_13_p, output tx_13_n, output tx_out_clk_13, input tx_clk_13, input [ 3:0] tx_charisk_13, input [31:0] tx_data_13, input [ 7:0] up_es_sel_13, input up_es_enb_13, input [11:0] up_es_addr_13, input up_es_wr_13, input [15:0] up_es_wdata_13, output [15:0] up_es_rdata_13, output up_es_ready_13, input up_rx_pll_rst_13, output up_rx_pll_locked_13, input up_rx_rst_13, input up_rx_user_ready_13, output up_rx_rst_done_13, input up_rx_lpm_dfe_n_13, input [ 2:0] up_rx_rate_13, input [ 1:0] up_rx_sys_clk_sel_13, input [ 2:0] up_rx_out_clk_sel_13, input [ 7:0] up_rx_sel_13, input up_rx_enb_13, input [11:0] up_rx_addr_13, input up_rx_wr_13, input [15:0] up_rx_wdata_13, output [15:0] up_rx_rdata_13, output up_rx_ready_13, input up_tx_pll_rst_13, output up_tx_pll_locked_13, input up_tx_rst_13, input up_tx_user_ready_13, output up_tx_rst_done_13, input up_tx_lpm_dfe_n_13, input [ 2:0] up_tx_rate_13, input [ 1:0] up_tx_sys_clk_sel_13, input [ 2:0] up_tx_out_clk_sel_13, input [ 7:0] up_tx_sel_13, input up_tx_enb_13, input [11:0] up_tx_addr_13, input up_tx_wr_13, input [15:0] up_tx_wdata_13, output [15:0] up_tx_rdata_13, output up_tx_ready_13, input cpll_ref_clk_14, input rx_14_p, input rx_14_n, output rx_out_clk_14, input rx_clk_14, output [ 3:0] rx_charisk_14, output [ 3:0] rx_disperr_14, output [ 3:0] rx_notintable_14, output [31:0] rx_data_14, input rx_calign_14, output tx_14_p, output tx_14_n, output tx_out_clk_14, input tx_clk_14, input [ 3:0] tx_charisk_14, input [31:0] tx_data_14, input [ 7:0] up_es_sel_14, input up_es_enb_14, input [11:0] up_es_addr_14, input up_es_wr_14, input [15:0] up_es_wdata_14, output [15:0] up_es_rdata_14, output up_es_ready_14, input up_rx_pll_rst_14, output up_rx_pll_locked_14, input up_rx_rst_14, input up_rx_user_ready_14, output up_rx_rst_done_14, input up_rx_lpm_dfe_n_14, input [ 2:0] up_rx_rate_14, input [ 1:0] up_rx_sys_clk_sel_14, input [ 2:0] up_rx_out_clk_sel_14, input [ 7:0] up_rx_sel_14, input up_rx_enb_14, input [11:0] up_rx_addr_14, input up_rx_wr_14, input [15:0] up_rx_wdata_14, output [15:0] up_rx_rdata_14, output up_rx_ready_14, input up_tx_pll_rst_14, output up_tx_pll_locked_14, input up_tx_rst_14, input up_tx_user_ready_14, output up_tx_rst_done_14, input up_tx_lpm_dfe_n_14, input [ 2:0] up_tx_rate_14, input [ 1:0] up_tx_sys_clk_sel_14, input [ 2:0] up_tx_out_clk_sel_14, input [ 7:0] up_tx_sel_14, input up_tx_enb_14, input [11:0] up_tx_addr_14, input up_tx_wr_14, input [15:0] up_tx_wdata_14, output [15:0] up_tx_rdata_14, output up_tx_ready_14, input cpll_ref_clk_15, input rx_15_p, input rx_15_n, output rx_out_clk_15, input rx_clk_15, output [ 3:0] rx_charisk_15, output [ 3:0] rx_disperr_15, output [ 3:0] rx_notintable_15, output [31:0] rx_data_15, input rx_calign_15, output tx_15_p, output tx_15_n, output tx_out_clk_15, input tx_clk_15, input [ 3:0] tx_charisk_15, input [31:0] tx_data_15, input [ 7:0] up_es_sel_15, input up_es_enb_15, input [11:0] up_es_addr_15, input up_es_wr_15, input [15:0] up_es_wdata_15, output [15:0] up_es_rdata_15, output up_es_ready_15, input up_rx_pll_rst_15, output up_rx_pll_locked_15, input up_rx_rst_15, input up_rx_user_ready_15, output up_rx_rst_done_15, input up_rx_lpm_dfe_n_15, input [ 2:0] up_rx_rate_15, input [ 1:0] up_rx_sys_clk_sel_15, input [ 2:0] up_rx_out_clk_sel_15, input [ 7:0] up_rx_sel_15, input up_rx_enb_15, input [11:0] up_rx_addr_15, input up_rx_wr_15, input [15:0] up_rx_wdata_15, output [15:0] up_rx_rdata_15, output up_rx_ready_15, input up_tx_pll_rst_15, output up_tx_pll_locked_15, input up_tx_rst_15, input up_tx_user_ready_15, output up_tx_rst_done_15, input up_tx_lpm_dfe_n_15, input [ 2:0] up_tx_rate_15, input [ 1:0] up_tx_sys_clk_sel_15, input [ 2:0] up_tx_out_clk_sel_15, input [ 7:0] up_tx_sel_15, input up_tx_enb_15, input [11:0] up_tx_addr_15, input up_tx_wr_15, input [15:0] up_tx_wdata_15, output [15:0] up_tx_rdata_15, output up_tx_ready_15); // parameters parameter integer XCVR_ID = 0; parameter integer GTH_OR_GTX_N = 0; parameter integer CPLL_TX_OR_RX_N = 0; parameter integer CPLL_FBDIV = 2; parameter integer QPLL_REFCLK_DIV = 2; parameter integer QPLL_FBDIV_RATIO = 1; parameter integer RX_OUT_DIV = 1; parameter integer RX_CLK25_DIV = 10; parameter integer RX_CLKBUF_ENABLE = 0; parameter integer TX_OUT_DIV = 1; parameter integer TX_CLK25_DIV = 10; parameter integer TX_CLKBUF_ENABLE = 0; parameter [31:0] PMA_RSV = 32'h00018480; parameter [72:0] RX_CDR_CFG = 72'h03000023ff20400020; parameter [26:0] QPLL_CFG = 27'h06801C1; parameter [ 9:0] QPLL_FBDIV = 10'b0000110000; // internal signals wire qpll2ch_clk_00; wire qpll2ch_ref_clk_00; wire qpll2ch_locked_00; wire up_qpll_rst_00; wire qpll2ch_clk_04; wire qpll2ch_ref_clk_04; wire qpll2ch_locked_04; wire up_qpll_rst_04; wire qpll2ch_clk_08; wire qpll2ch_ref_clk_08; wire qpll2ch_locked_08; wire up_qpll_rst_08; wire qpll2ch_clk_12; wire qpll2ch_ref_clk_12; wire qpll2ch_locked_12; wire up_qpll_rst_12; // quad controls assign up_qpll_rst_00 = (CPLL_TX_OR_RX_N == 0) ? up_tx_00.pll_rst : up_rx_00.pll_rst; assign up_qpll_rst_04 = (CPLL_TX_OR_RX_N == 0) ? up_tx_04.pll_rst : up_rx_04.pll_rst; assign up_qpll_rst_08 = (CPLL_TX_OR_RX_N == 0) ? up_tx_08.pll_rst : up_rx_08.pll_rst; assign up_qpll_rst_12 = (CPLL_TX_OR_RX_N == 0) ? up_tx_12.pll_rst : up_rx_12.pll_rst; // instantiations generate if (NUM_OF_LANES >= 1) begin util_adxcvr_xcm #( .XCVR_ID (n), .GTH_OR_GTX_N (GTH_OR_GTX_N), .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV), .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), .QPLL_CFG (QPLL_CFG), .QPLL_FBDIV (QPLL_FBDIV)) i_xcm_00 ( .qpll_ref_clk (qpll_ref_clk_00), .qpll2ch_clk (qpll2ch_clk_00), .qpll2ch_ref_clk (qpll2ch_ref_clk_00), .qpll2ch_locked (qpll2ch_locked_00), .up_rstn (up_rstn), .up_clk (up_clk), .up_qpll_rst (up_qpll_rst_00), .up_cm_sel (up_cm_sel_00), .up_cm_enb (up_cm_enb_00), .up_cm_addr (up_cm_addr_00), .up_cm_wr (up_cm_wr_00), .up_cm_wdata (up_cm_wdata_00), .up_cm_rdata (up_cm_rdata_00), .up_cm_ready (up_cm_ready_00)); end endgenerate generate if (NUM_OF_LANES >= 1) begin util_adxcvr_xch #( .XCVR_ID (n), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE), .PMA_RSV (PMA_RSV), .RX_CDR_CFG (RX_CDR_CFG)) i_xch_00 ( .qpll2ch_clk (qpll2ch_clk_00), .qpll2ch_ref_clk (qpll2ch_ref_clk_00), .qpll2ch_locked (qpll2ch_locked_00), .cpll_ref_clk (cpll_ref_clk_00), .rx_p (rx_00_p), .rx_n (rx_00_n), .rx_out_clk (rx_out_clk_00), .rx_clk (rx_clk_00), .rx_charisk (rx_charisk_00), .rx_disperr (rx_disperr_00), .rx_notintable (rx_notintable_00), .rx_data (rx_data_00), .rx_calign (rx_calign_00), .tx_p (tx_00_p), .tx_n (tx_00_n), .tx_out_clk (tx_out_clk_00), .tx_clk (tx_clk_00), .tx_charisk (tx_charisk_00), .tx_data (tx_data_00), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_sel (up_es_sel_00), .up_es_enb (up_es_enb_00), .up_es_addr (up_es_addr_00), .up_es_wr (up_es_wr_00), .up_es_wdata (up_es_wdata_00), .up_es_rdata (up_es_rdata_00), .up_es_ready (up_es_ready_00), .up_rx_pll_rst (up_rx_pll_rst_00), .up_rx_pll_locked (up_rx_pll_locked_00), .up_rx_rst (up_rx_rst_00), .up_rx_user_ready (up_rx_user_ready_00), .up_rx_rst_done (up_rx_rst_done_00), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_00), .up_rx_rate (up_rx_rate_00), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_00), .up_rx_out_clk_sel (up_rx_out_clk_sel_00), .up_rx_sel (up_rx_sel_00), .up_rx_enb (up_rx_enb_00), .up_rx_addr (up_rx_addr_00), .up_rx_wr (up_rx_wr_00), .up_rx_wdata (up_rx_wdata_00), .up_rx_rdata (up_rx_rdata_00), .up_rx_ready (up_rx_ready_00), .up_tx_pll_rst (up_tx_pll_rst_00), .up_tx_pll_locked (up_tx_pll_locked_00), .up_tx_rst (up_tx_rst_00), .up_tx_user_ready (up_tx_user_ready_00), .up_tx_rst_done (up_tx_rst_done_00), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_00), .up_tx_rate (up_tx_rate_00), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_00), .up_tx_out_clk_sel (up_tx_out_clk_sel_00), .up_tx_sel (up_tx_sel_00), .up_tx_enb (up_tx_enb_00), .up_tx_addr (up_tx_addr_00), .up_tx_wr (up_tx_wr_00), .up_tx_wdata (up_tx_wdata_00), .up_tx_rdata (up_tx_rdata_00), .up_tx_ready (up_tx_ready_00)); end endgenerate generate if (NUM_OF_LANES >= 2) begin util_adxcvr_xch #( .XCVR_ID (n), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE), .PMA_RSV (PMA_RSV), .RX_CDR_CFG (RX_CDR_CFG)) i_xch_01 ( .qpll2ch_clk (qpll2ch_clk_00), .qpll2ch_ref_clk (qpll2ch_ref_clk_00), .qpll2ch_locked (qpll2ch_locked_00), .cpll_ref_clk (cpll_ref_clk_01), .rx_p (rx_01_p), .rx_n (rx_01_n), .rx_out_clk (rx_out_clk_01), .rx_clk (rx_clk_01), .rx_charisk (rx_charisk_01), .rx_disperr (rx_disperr_01), .rx_notintable (rx_notintable_01), .rx_data (rx_data_01), .rx_calign (rx_calign_01), .tx_p (tx_01_p), .tx_n (tx_01_n), .tx_out_clk (tx_out_clk_01), .tx_clk (tx_clk_01), .tx_charisk (tx_charisk_01), .tx_data (tx_data_01), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_sel (up_es_sel_01), .up_es_enb (up_es_enb_01), .up_es_addr (up_es_addr_01), .up_es_wr (up_es_wr_01), .up_es_wdata (up_es_wdata_01), .up_es_rdata (up_es_rdata_01), .up_es_ready (up_es_ready_01), .up_rx_pll_rst (up_rx_pll_rst_01), .up_rx_pll_locked (up_rx_pll_locked_01), .up_rx_rst (up_rx_rst_01), .up_rx_user_ready (up_rx_user_ready_01), .up_rx_rst_done (up_rx_rst_done_01), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_01), .up_rx_rate (up_rx_rate_01), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_01), .up_rx_out_clk_sel (up_rx_out_clk_sel_01), .up_rx_sel (up_rx_sel_01), .up_rx_enb (up_rx_enb_01), .up_rx_addr (up_rx_addr_01), .up_rx_wr (up_rx_wr_01), .up_rx_wdata (up_rx_wdata_01), .up_rx_rdata (up_rx_rdata_01), .up_rx_ready (up_rx_ready_01), .up_tx_pll_rst (up_tx_pll_rst_01), .up_tx_pll_locked (up_tx_pll_locked_01), .up_tx_rst (up_tx_rst_01), .up_tx_user_ready (up_tx_user_ready_01), .up_tx_rst_done (up_tx_rst_done_01), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_01), .up_tx_rate (up_tx_rate_01), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_01), .up_tx_out_clk_sel (up_tx_out_clk_sel_01), .up_tx_sel (up_tx_sel_01), .up_tx_enb (up_tx_enb_01), .up_tx_addr (up_tx_addr_01), .up_tx_wr (up_tx_wr_01), .up_tx_wdata (up_tx_wdata_01), .up_tx_rdata (up_tx_rdata_01), .up_tx_ready (up_tx_ready_01)); end endgenerate generate if (NUM_OF_LANES >= 3) begin util_adxcvr_xch #( .XCVR_ID (n), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE), .PMA_RSV (PMA_RSV), .RX_CDR_CFG (RX_CDR_CFG)) i_xch_02 ( .qpll2ch_clk (qpll2ch_clk_00), .qpll2ch_ref_clk (qpll2ch_ref_clk_00), .qpll2ch_locked (qpll2ch_locked_00), .cpll_ref_clk (cpll_ref_clk_02), .rx_p (rx_02_p), .rx_n (rx_02_n), .rx_out_clk (rx_out_clk_02), .rx_clk (rx_clk_02), .rx_charisk (rx_charisk_02), .rx_disperr (rx_disperr_02), .rx_notintable (rx_notintable_02), .rx_data (rx_data_02), .rx_calign (rx_calign_02), .tx_p (tx_02_p), .tx_n (tx_02_n), .tx_out_clk (tx_out_clk_02), .tx_clk (tx_clk_02), .tx_charisk (tx_charisk_02), .tx_data (tx_data_02), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_sel (up_es_sel_02), .up_es_enb (up_es_enb_02), .up_es_addr (up_es_addr_02), .up_es_wr (up_es_wr_02), .up_es_wdata (up_es_wdata_02), .up_es_rdata (up_es_rdata_02), .up_es_ready (up_es_ready_02), .up_rx_pll_rst (up_rx_pll_rst_02), .up_rx_pll_locked (up_rx_pll_locked_02), .up_rx_rst (up_rx_rst_02), .up_rx_user_ready (up_rx_user_ready_02), .up_rx_rst_done (up_rx_rst_done_02), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_02), .up_rx_rate (up_rx_rate_02), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_02), .up_rx_out_clk_sel (up_rx_out_clk_sel_02), .up_rx_sel (up_rx_sel_02), .up_rx_enb (up_rx_enb_02), .up_rx_addr (up_rx_addr_02), .up_rx_wr (up_rx_wr_02), .up_rx_wdata (up_rx_wdata_02), .up_rx_rdata (up_rx_rdata_02), .up_rx_ready (up_rx_ready_02), .up_tx_pll_rst (up_tx_pll_rst_02), .up_tx_pll_locked (up_tx_pll_locked_02), .up_tx_rst (up_tx_rst_02), .up_tx_user_ready (up_tx_user_ready_02), .up_tx_rst_done (up_tx_rst_done_02), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_02), .up_tx_rate (up_tx_rate_02), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_02), .up_tx_out_clk_sel (up_tx_out_clk_sel_02), .up_tx_sel (up_tx_sel_02), .up_tx_enb (up_tx_enb_02), .up_tx_addr (up_tx_addr_02), .up_tx_wr (up_tx_wr_02), .up_tx_wdata (up_tx_wdata_02), .up_tx_rdata (up_tx_rdata_02), .up_tx_ready (up_tx_ready_02)); end endgenerate generate if (NUM_OF_LANES >= 4) begin util_adxcvr_xch #( .XCVR_ID (n), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE), .PMA_RSV (PMA_RSV), .RX_CDR_CFG (RX_CDR_CFG)) i_xch_03 ( .qpll2ch_clk (qpll2ch_clk_00), .qpll2ch_ref_clk (qpll2ch_ref_clk_00), .qpll2ch_locked (qpll2ch_locked_00), .cpll_ref_clk (cpll_ref_clk_03), .rx_p (rx_03_p), .rx_n (rx_03_n), .rx_out_clk (rx_out_clk_03), .rx_clk (rx_clk_03), .rx_charisk (rx_charisk_03), .rx_disperr (rx_disperr_03), .rx_notintable (rx_notintable_03), .rx_data (rx_data_03), .rx_calign (rx_calign_03), .tx_p (tx_03_p), .tx_n (tx_03_n), .tx_out_clk (tx_out_clk_03), .tx_clk (tx_clk_03), .tx_charisk (tx_charisk_03), .tx_data (tx_data_03), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_sel (up_es_sel_03), .up_es_enb (up_es_enb_03), .up_es_addr (up_es_addr_03), .up_es_wr (up_es_wr_03), .up_es_wdata (up_es_wdata_03), .up_es_rdata (up_es_rdata_03), .up_es_ready (up_es_ready_03), .up_rx_pll_rst (up_rx_pll_rst_03), .up_rx_pll_locked (up_rx_pll_locked_03), .up_rx_rst (up_rx_rst_03), .up_rx_user_ready (up_rx_user_ready_03), .up_rx_rst_done (up_rx_rst_done_03), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_03), .up_rx_rate (up_rx_rate_03), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_03), .up_rx_out_clk_sel (up_rx_out_clk_sel_03), .up_rx_sel (up_rx_sel_03), .up_rx_enb (up_rx_enb_03), .up_rx_addr (up_rx_addr_03), .up_rx_wr (up_rx_wr_03), .up_rx_wdata (up_rx_wdata_03), .up_rx_rdata (up_rx_rdata_03), .up_rx_ready (up_rx_ready_03), .up_tx_pll_rst (up_tx_pll_rst_03), .up_tx_pll_locked (up_tx_pll_locked_03), .up_tx_rst (up_tx_rst_03), .up_tx_user_ready (up_tx_user_ready_03), .up_tx_rst_done (up_tx_rst_done_03), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_03), .up_tx_rate (up_tx_rate_03), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_03), .up_tx_out_clk_sel (up_tx_out_clk_sel_03), .up_tx_sel (up_tx_sel_03), .up_tx_enb (up_tx_enb_03), .up_tx_addr (up_tx_addr_03), .up_tx_wr (up_tx_wr_03), .up_tx_wdata (up_tx_wdata_03), .up_tx_rdata (up_tx_rdata_03), .up_tx_ready (up_tx_ready_03)); end endgenerate generate if (NUM_OF_LANES >= 5) begin util_adxcvr_xcm #( .XCVR_ID (n), .GTH_OR_GTX_N (GTH_OR_GTX_N), .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV), .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), .QPLL_CFG (QPLL_CFG), .QPLL_FBDIV (QPLL_FBDIV)) i_xcm_04 ( .qpll_ref_clk (qpll_ref_clk_04), .qpll2ch_clk (qpll2ch_clk_04), .qpll2ch_ref_clk (qpll2ch_ref_clk_04), .qpll2ch_locked (qpll2ch_locked_04), .up_rstn (up_rstn), .up_clk (up_clk), .up_qpll_rst (up_qpll_rst_04), .up_cm_sel (up_cm_sel_04), .up_cm_enb (up_cm_enb_04), .up_cm_addr (up_cm_addr_04), .up_cm_wr (up_cm_wr_04), .up_cm_wdata (up_cm_wdata_04), .up_cm_rdata (up_cm_rdata_04), .up_cm_ready (up_cm_ready_04)); end endgenerate generate if (NUM_OF_LANES >= 5) begin util_adxcvr_xch #( .XCVR_ID (n), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE), .PMA_RSV (PMA_RSV), .RX_CDR_CFG (RX_CDR_CFG)) i_xch_04 ( .qpll2ch_clk (qpll2ch_clk_04), .qpll2ch_ref_clk (qpll2ch_ref_clk_04), .qpll2ch_locked (qpll2ch_locked_04), .cpll_ref_clk (cpll_ref_clk_04), .rx_p (rx_04_p), .rx_n (rx_04_n), .rx_out_clk (rx_out_clk_04), .rx_clk (rx_clk_04), .rx_charisk (rx_charisk_04), .rx_disperr (rx_disperr_04), .rx_notintable (rx_notintable_04), .rx_data (rx_data_04), .rx_calign (rx_calign_04), .tx_p (tx_04_p), .tx_n (tx_04_n), .tx_out_clk (tx_out_clk_04), .tx_clk (tx_clk_04), .tx_charisk (tx_charisk_04), .tx_data (tx_data_04), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_sel (up_es_sel_04), .up_es_enb (up_es_enb_04), .up_es_addr (up_es_addr_04), .up_es_wr (up_es_wr_04), .up_es_wdata (up_es_wdata_04), .up_es_rdata (up_es_rdata_04), .up_es_ready (up_es_ready_04), .up_rx_pll_rst (up_rx_pll_rst_04), .up_rx_pll_locked (up_rx_pll_locked_04), .up_rx_rst (up_rx_rst_04), .up_rx_user_ready (up_rx_user_ready_04), .up_rx_rst_done (up_rx_rst_done_04), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_04), .up_rx_rate (up_rx_rate_04), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_04), .up_rx_out_clk_sel (up_rx_out_clk_sel_04), .up_rx_sel (up_rx_sel_04), .up_rx_enb (up_rx_enb_04), .up_rx_addr (up_rx_addr_04), .up_rx_wr (up_rx_wr_04), .up_rx_wdata (up_rx_wdata_04), .up_rx_rdata (up_rx_rdata_04), .up_rx_ready (up_rx_ready_04), .up_tx_pll_rst (up_tx_pll_rst_04), .up_tx_pll_locked (up_tx_pll_locked_04), .up_tx_rst (up_tx_rst_04), .up_tx_user_ready (up_tx_user_ready_04), .up_tx_rst_done (up_tx_rst_done_04), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_04), .up_tx_rate (up_tx_rate_04), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_04), .up_tx_out_clk_sel (up_tx_out_clk_sel_04), .up_tx_sel (up_tx_sel_04), .up_tx_enb (up_tx_enb_04), .up_tx_addr (up_tx_addr_04), .up_tx_wr (up_tx_wr_04), .up_tx_wdata (up_tx_wdata_04), .up_tx_rdata (up_tx_rdata_04), .up_tx_ready (up_tx_ready_04)); end endgenerate generate if (NUM_OF_LANES >= 6) begin util_adxcvr_xch #( .XCVR_ID (n), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE), .PMA_RSV (PMA_RSV), .RX_CDR_CFG (RX_CDR_CFG)) i_xch_05 ( .qpll2ch_clk (qpll2ch_clk_04), .qpll2ch_ref_clk (qpll2ch_ref_clk_04), .qpll2ch_locked (qpll2ch_locked_04), .cpll_ref_clk (cpll_ref_clk_05), .rx_p (rx_05_p), .rx_n (rx_05_n), .rx_out_clk (rx_out_clk_05), .rx_clk (rx_clk_05), .rx_charisk (rx_charisk_05), .rx_disperr (rx_disperr_05), .rx_notintable (rx_notintable_05), .rx_data (rx_data_05), .rx_calign (rx_calign_05), .tx_p (tx_05_p), .tx_n (tx_05_n), .tx_out_clk (tx_out_clk_05), .tx_clk (tx_clk_05), .tx_charisk (tx_charisk_05), .tx_data (tx_data_05), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_sel (up_es_sel_05), .up_es_enb (up_es_enb_05), .up_es_addr (up_es_addr_05), .up_es_wr (up_es_wr_05), .up_es_wdata (up_es_wdata_05), .up_es_rdata (up_es_rdata_05), .up_es_ready (up_es_ready_05), .up_rx_pll_rst (up_rx_pll_rst_05), .up_rx_pll_locked (up_rx_pll_locked_05), .up_rx_rst (up_rx_rst_05), .up_rx_user_ready (up_rx_user_ready_05), .up_rx_rst_done (up_rx_rst_done_05), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_05), .up_rx_rate (up_rx_rate_05), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_05), .up_rx_out_clk_sel (up_rx_out_clk_sel_05), .up_rx_sel (up_rx_sel_05), .up_rx_enb (up_rx_enb_05), .up_rx_addr (up_rx_addr_05), .up_rx_wr (up_rx_wr_05), .up_rx_wdata (up_rx_wdata_05), .up_rx_rdata (up_rx_rdata_05), .up_rx_ready (up_rx_ready_05), .up_tx_pll_rst (up_tx_pll_rst_05), .up_tx_pll_locked (up_tx_pll_locked_05), .up_tx_rst (up_tx_rst_05), .up_tx_user_ready (up_tx_user_ready_05), .up_tx_rst_done (up_tx_rst_done_05), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_05), .up_tx_rate (up_tx_rate_05), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_05), .up_tx_out_clk_sel (up_tx_out_clk_sel_05), .up_tx_sel (up_tx_sel_05), .up_tx_enb (up_tx_enb_05), .up_tx_addr (up_tx_addr_05), .up_tx_wr (up_tx_wr_05), .up_tx_wdata (up_tx_wdata_05), .up_tx_rdata (up_tx_rdata_05), .up_tx_ready (up_tx_ready_05)); end endgenerate generate if (NUM_OF_LANES >= 7) begin util_adxcvr_xch #( .XCVR_ID (n), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE), .PMA_RSV (PMA_RSV), .RX_CDR_CFG (RX_CDR_CFG)) i_xch_06 ( .qpll2ch_clk (qpll2ch_clk_04), .qpll2ch_ref_clk (qpll2ch_ref_clk_04), .qpll2ch_locked (qpll2ch_locked_04), .cpll_ref_clk (cpll_ref_clk_06), .rx_p (rx_06_p), .rx_n (rx_06_n), .rx_out_clk (rx_out_clk_06), .rx_clk (rx_clk_06), .rx_charisk (rx_charisk_06), .rx_disperr (rx_disperr_06), .rx_notintable (rx_notintable_06), .rx_data (rx_data_06), .rx_calign (rx_calign_06), .tx_p (tx_06_p), .tx_n (tx_06_n), .tx_out_clk (tx_out_clk_06), .tx_clk (tx_clk_06), .tx_charisk (tx_charisk_06), .tx_data (tx_data_06), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_sel (up_es_sel_06), .up_es_enb (up_es_enb_06), .up_es_addr (up_es_addr_06), .up_es_wr (up_es_wr_06), .up_es_wdata (up_es_wdata_06), .up_es_rdata (up_es_rdata_06), .up_es_ready (up_es_ready_06), .up_rx_pll_rst (up_rx_pll_rst_06), .up_rx_pll_locked (up_rx_pll_locked_06), .up_rx_rst (up_rx_rst_06), .up_rx_user_ready (up_rx_user_ready_06), .up_rx_rst_done (up_rx_rst_done_06), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_06), .up_rx_rate (up_rx_rate_06), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_06), .up_rx_out_clk_sel (up_rx_out_clk_sel_06), .up_rx_sel (up_rx_sel_06), .up_rx_enb (up_rx_enb_06), .up_rx_addr (up_rx_addr_06), .up_rx_wr (up_rx_wr_06), .up_rx_wdata (up_rx_wdata_06), .up_rx_rdata (up_rx_rdata_06), .up_rx_ready (up_rx_ready_06), .up_tx_pll_rst (up_tx_pll_rst_06), .up_tx_pll_locked (up_tx_pll_locked_06), .up_tx_rst (up_tx_rst_06), .up_tx_user_ready (up_tx_user_ready_06), .up_tx_rst_done (up_tx_rst_done_06), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_06), .up_tx_rate (up_tx_rate_06), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_06), .up_tx_out_clk_sel (up_tx_out_clk_sel_06), .up_tx_sel (up_tx_sel_06), .up_tx_enb (up_tx_enb_06), .up_tx_addr (up_tx_addr_06), .up_tx_wr (up_tx_wr_06), .up_tx_wdata (up_tx_wdata_06), .up_tx_rdata (up_tx_rdata_06), .up_tx_ready (up_tx_ready_06)); end endgenerate generate if (NUM_OF_LANES >= 8) begin util_adxcvr_xch #( .XCVR_ID (n), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE), .PMA_RSV (PMA_RSV), .RX_CDR_CFG (RX_CDR_CFG)) i_xch_07 ( .qpll2ch_clk (qpll2ch_clk_04), .qpll2ch_ref_clk (qpll2ch_ref_clk_04), .qpll2ch_locked (qpll2ch_locked_04), .cpll_ref_clk (cpll_ref_clk_07), .rx_p (rx_07_p), .rx_n (rx_07_n), .rx_out_clk (rx_out_clk_07), .rx_clk (rx_clk_07), .rx_charisk (rx_charisk_07), .rx_disperr (rx_disperr_07), .rx_notintable (rx_notintable_07), .rx_data (rx_data_07), .rx_calign (rx_calign_07), .tx_p (tx_07_p), .tx_n (tx_07_n), .tx_out_clk (tx_out_clk_07), .tx_clk (tx_clk_07), .tx_charisk (tx_charisk_07), .tx_data (tx_data_07), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_sel (up_es_sel_07), .up_es_enb (up_es_enb_07), .up_es_addr (up_es_addr_07), .up_es_wr (up_es_wr_07), .up_es_wdata (up_es_wdata_07), .up_es_rdata (up_es_rdata_07), .up_es_ready (up_es_ready_07), .up_rx_pll_rst (up_rx_pll_rst_07), .up_rx_pll_locked (up_rx_pll_locked_07), .up_rx_rst (up_rx_rst_07), .up_rx_user_ready (up_rx_user_ready_07), .up_rx_rst_done (up_rx_rst_done_07), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_07), .up_rx_rate (up_rx_rate_07), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_07), .up_rx_out_clk_sel (up_rx_out_clk_sel_07), .up_rx_sel (up_rx_sel_07), .up_rx_enb (up_rx_enb_07), .up_rx_addr (up_rx_addr_07), .up_rx_wr (up_rx_wr_07), .up_rx_wdata (up_rx_wdata_07), .up_rx_rdata (up_rx_rdata_07), .up_rx_ready (up_rx_ready_07), .up_tx_pll_rst (up_tx_pll_rst_07), .up_tx_pll_locked (up_tx_pll_locked_07), .up_tx_rst (up_tx_rst_07), .up_tx_user_ready (up_tx_user_ready_07), .up_tx_rst_done (up_tx_rst_done_07), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_07), .up_tx_rate (up_tx_rate_07), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_07), .up_tx_out_clk_sel (up_tx_out_clk_sel_07), .up_tx_sel (up_tx_sel_07), .up_tx_enb (up_tx_enb_07), .up_tx_addr (up_tx_addr_07), .up_tx_wr (up_tx_wr_07), .up_tx_wdata (up_tx_wdata_07), .up_tx_rdata (up_tx_rdata_07), .up_tx_ready (up_tx_ready_07)); end endgenerate generate if (NUM_OF_LANES >= 9) begin util_adxcvr_xcm #( .XCVR_ID (n), .GTH_OR_GTX_N (GTH_OR_GTX_N), .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV), .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), .QPLL_CFG (QPLL_CFG), .QPLL_FBDIV (QPLL_FBDIV)) i_xcm_08 ( .qpll_ref_clk (qpll_ref_clk_08), .qpll2ch_clk (qpll2ch_clk_08), .qpll2ch_ref_clk (qpll2ch_ref_clk_08), .qpll2ch_locked (qpll2ch_locked_08), .up_rstn (up_rstn), .up_clk (up_clk), .up_qpll_rst (up_qpll_rst_08), .up_cm_sel (up_cm_sel_08), .up_cm_enb (up_cm_enb_08), .up_cm_addr (up_cm_addr_08), .up_cm_wr (up_cm_wr_08), .up_cm_wdata (up_cm_wdata_08), .up_cm_rdata (up_cm_rdata_08), .up_cm_ready (up_cm_ready_08)); end endgenerate generate if (NUM_OF_LANES >= 9) begin util_adxcvr_xch #( .XCVR_ID (n), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE), .PMA_RSV (PMA_RSV), .RX_CDR_CFG (RX_CDR_CFG)) i_xch_08 ( .qpll2ch_clk (qpll2ch_clk_08), .qpll2ch_ref_clk (qpll2ch_ref_clk_08), .qpll2ch_locked (qpll2ch_locked_08), .cpll_ref_clk (cpll_ref_clk_08), .rx_p (rx_08_p), .rx_n (rx_08_n), .rx_out_clk (rx_out_clk_08), .rx_clk (rx_clk_08), .rx_charisk (rx_charisk_08), .rx_disperr (rx_disperr_08), .rx_notintable (rx_notintable_08), .rx_data (rx_data_08), .rx_calign (rx_calign_08), .tx_p (tx_08_p), .tx_n (tx_08_n), .tx_out_clk (tx_out_clk_08), .tx_clk (tx_clk_08), .tx_charisk (tx_charisk_08), .tx_data (tx_data_08), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_sel (up_es_sel_08), .up_es_enb (up_es_enb_08), .up_es_addr (up_es_addr_08), .up_es_wr (up_es_wr_08), .up_es_wdata (up_es_wdata_08), .up_es_rdata (up_es_rdata_08), .up_es_ready (up_es_ready_08), .up_rx_pll_rst (up_rx_pll_rst_08), .up_rx_pll_locked (up_rx_pll_locked_08), .up_rx_rst (up_rx_rst_08), .up_rx_user_ready (up_rx_user_ready_08), .up_rx_rst_done (up_rx_rst_done_08), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_08), .up_rx_rate (up_rx_rate_08), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_08), .up_rx_out_clk_sel (up_rx_out_clk_sel_08), .up_rx_sel (up_rx_sel_08), .up_rx_enb (up_rx_enb_08), .up_rx_addr (up_rx_addr_08), .up_rx_wr (up_rx_wr_08), .up_rx_wdata (up_rx_wdata_08), .up_rx_rdata (up_rx_rdata_08), .up_rx_ready (up_rx_ready_08), .up_tx_pll_rst (up_tx_pll_rst_08), .up_tx_pll_locked (up_tx_pll_locked_08), .up_tx_rst (up_tx_rst_08), .up_tx_user_ready (up_tx_user_ready_08), .up_tx_rst_done (up_tx_rst_done_08), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_08), .up_tx_rate (up_tx_rate_08), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_08), .up_tx_out_clk_sel (up_tx_out_clk_sel_08), .up_tx_sel (up_tx_sel_08), .up_tx_enb (up_tx_enb_08), .up_tx_addr (up_tx_addr_08), .up_tx_wr (up_tx_wr_08), .up_tx_wdata (up_tx_wdata_08), .up_tx_rdata (up_tx_rdata_08), .up_tx_ready (up_tx_ready_08)); end endgenerate generate if (NUM_OF_LANES >= 10) begin util_adxcvr_xch #( .XCVR_ID (n), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE), .PMA_RSV (PMA_RSV), .RX_CDR_CFG (RX_CDR_CFG)) i_xch_09 ( .qpll2ch_clk (qpll2ch_clk_08), .qpll2ch_ref_clk (qpll2ch_ref_clk_08), .qpll2ch_locked (qpll2ch_locked_08), .cpll_ref_clk (cpll_ref_clk_09), .rx_p (rx_09_p), .rx_n (rx_09_n), .rx_out_clk (rx_out_clk_09), .rx_clk (rx_clk_09), .rx_charisk (rx_charisk_09), .rx_disperr (rx_disperr_09), .rx_notintable (rx_notintable_09), .rx_data (rx_data_09), .rx_calign (rx_calign_09), .tx_p (tx_09_p), .tx_n (tx_09_n), .tx_out_clk (tx_out_clk_09), .tx_clk (tx_clk_09), .tx_charisk (tx_charisk_09), .tx_data (tx_data_09), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_sel (up_es_sel_09), .up_es_enb (up_es_enb_09), .up_es_addr (up_es_addr_09), .up_es_wr (up_es_wr_09), .up_es_wdata (up_es_wdata_09), .up_es_rdata (up_es_rdata_09), .up_es_ready (up_es_ready_09), .up_rx_pll_rst (up_rx_pll_rst_09), .up_rx_pll_locked (up_rx_pll_locked_09), .up_rx_rst (up_rx_rst_09), .up_rx_user_ready (up_rx_user_ready_09), .up_rx_rst_done (up_rx_rst_done_09), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_09), .up_rx_rate (up_rx_rate_09), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_09), .up_rx_out_clk_sel (up_rx_out_clk_sel_09), .up_rx_sel (up_rx_sel_09), .up_rx_enb (up_rx_enb_09), .up_rx_addr (up_rx_addr_09), .up_rx_wr (up_rx_wr_09), .up_rx_wdata (up_rx_wdata_09), .up_rx_rdata (up_rx_rdata_09), .up_rx_ready (up_rx_ready_09), .up_tx_pll_rst (up_tx_pll_rst_09), .up_tx_pll_locked (up_tx_pll_locked_09), .up_tx_rst (up_tx_rst_09), .up_tx_user_ready (up_tx_user_ready_09), .up_tx_rst_done (up_tx_rst_done_09), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_09), .up_tx_rate (up_tx_rate_09), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_09), .up_tx_out_clk_sel (up_tx_out_clk_sel_09), .up_tx_sel (up_tx_sel_09), .up_tx_enb (up_tx_enb_09), .up_tx_addr (up_tx_addr_09), .up_tx_wr (up_tx_wr_09), .up_tx_wdata (up_tx_wdata_09), .up_tx_rdata (up_tx_rdata_09), .up_tx_ready (up_tx_ready_09)); end endgenerate generate if (NUM_OF_LANES >= 11) begin util_adxcvr_xch #( .XCVR_ID (n), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE), .PMA_RSV (PMA_RSV), .RX_CDR_CFG (RX_CDR_CFG)) i_xch_10 ( .qpll2ch_clk (qpll2ch_clk_08), .qpll2ch_ref_clk (qpll2ch_ref_clk_08), .qpll2ch_locked (qpll2ch_locked_08), .cpll_ref_clk (cpll_ref_clk_10), .rx_p (rx_10_p), .rx_n (rx_10_n), .rx_out_clk (rx_out_clk_10), .rx_clk (rx_clk_10), .rx_charisk (rx_charisk_10), .rx_disperr (rx_disperr_10), .rx_notintable (rx_notintable_10), .rx_data (rx_data_10), .rx_calign (rx_calign_10), .tx_p (tx_10_p), .tx_n (tx_10_n), .tx_out_clk (tx_out_clk_10), .tx_clk (tx_clk_10), .tx_charisk (tx_charisk_10), .tx_data (tx_data_10), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_sel (up_es_sel_10), .up_es_enb (up_es_enb_10), .up_es_addr (up_es_addr_10), .up_es_wr (up_es_wr_10), .up_es_wdata (up_es_wdata_10), .up_es_rdata (up_es_rdata_10), .up_es_ready (up_es_ready_10), .up_rx_pll_rst (up_rx_pll_rst_10), .up_rx_pll_locked (up_rx_pll_locked_10), .up_rx_rst (up_rx_rst_10), .up_rx_user_ready (up_rx_user_ready_10), .up_rx_rst_done (up_rx_rst_done_10), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_10), .up_rx_rate (up_rx_rate_10), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_10), .up_rx_out_clk_sel (up_rx_out_clk_sel_10), .up_rx_sel (up_rx_sel_10), .up_rx_enb (up_rx_enb_10), .up_rx_addr (up_rx_addr_10), .up_rx_wr (up_rx_wr_10), .up_rx_wdata (up_rx_wdata_10), .up_rx_rdata (up_rx_rdata_10), .up_rx_ready (up_rx_ready_10), .up_tx_pll_rst (up_tx_pll_rst_10), .up_tx_pll_locked (up_tx_pll_locked_10), .up_tx_rst (up_tx_rst_10), .up_tx_user_ready (up_tx_user_ready_10), .up_tx_rst_done (up_tx_rst_done_10), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_10), .up_tx_rate (up_tx_rate_10), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_10), .up_tx_out_clk_sel (up_tx_out_clk_sel_10), .up_tx_sel (up_tx_sel_10), .up_tx_enb (up_tx_enb_10), .up_tx_addr (up_tx_addr_10), .up_tx_wr (up_tx_wr_10), .up_tx_wdata (up_tx_wdata_10), .up_tx_rdata (up_tx_rdata_10), .up_tx_ready (up_tx_ready_10)); end endgenerate generate if (NUM_OF_LANES >= 12) begin util_adxcvr_xch #( .XCVR_ID (n), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE), .PMA_RSV (PMA_RSV), .RX_CDR_CFG (RX_CDR_CFG)) i_xch_11 ( .qpll2ch_clk (qpll2ch_clk_08), .qpll2ch_ref_clk (qpll2ch_ref_clk_08), .qpll2ch_locked (qpll2ch_locked_08), .cpll_ref_clk (cpll_ref_clk_11), .rx_p (rx_11_p), .rx_n (rx_11_n), .rx_out_clk (rx_out_clk_11), .rx_clk (rx_clk_11), .rx_charisk (rx_charisk_11), .rx_disperr (rx_disperr_11), .rx_notintable (rx_notintable_11), .rx_data (rx_data_11), .rx_calign (rx_calign_11), .tx_p (tx_11_p), .tx_n (tx_11_n), .tx_out_clk (tx_out_clk_11), .tx_clk (tx_clk_11), .tx_charisk (tx_charisk_11), .tx_data (tx_data_11), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_sel (up_es_sel_11), .up_es_enb (up_es_enb_11), .up_es_addr (up_es_addr_11), .up_es_wr (up_es_wr_11), .up_es_wdata (up_es_wdata_11), .up_es_rdata (up_es_rdata_11), .up_es_ready (up_es_ready_11), .up_rx_pll_rst (up_rx_pll_rst_11), .up_rx_pll_locked (up_rx_pll_locked_11), .up_rx_rst (up_rx_rst_11), .up_rx_user_ready (up_rx_user_ready_11), .up_rx_rst_done (up_rx_rst_done_11), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_11), .up_rx_rate (up_rx_rate_11), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_11), .up_rx_out_clk_sel (up_rx_out_clk_sel_11), .up_rx_sel (up_rx_sel_11), .up_rx_enb (up_rx_enb_11), .up_rx_addr (up_rx_addr_11), .up_rx_wr (up_rx_wr_11), .up_rx_wdata (up_rx_wdata_11), .up_rx_rdata (up_rx_rdata_11), .up_rx_ready (up_rx_ready_11), .up_tx_pll_rst (up_tx_pll_rst_11), .up_tx_pll_locked (up_tx_pll_locked_11), .up_tx_rst (up_tx_rst_11), .up_tx_user_ready (up_tx_user_ready_11), .up_tx_rst_done (up_tx_rst_done_11), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_11), .up_tx_rate (up_tx_rate_11), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_11), .up_tx_out_clk_sel (up_tx_out_clk_sel_11), .up_tx_sel (up_tx_sel_11), .up_tx_enb (up_tx_enb_11), .up_tx_addr (up_tx_addr_11), .up_tx_wr (up_tx_wr_11), .up_tx_wdata (up_tx_wdata_11), .up_tx_rdata (up_tx_rdata_11), .up_tx_ready (up_tx_ready_11)); end endgenerate generate if (NUM_OF_LANES >= 13) begin util_adxcvr_xcm #( .XCVR_ID (n), .GTH_OR_GTX_N (GTH_OR_GTX_N), .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV), .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), .QPLL_CFG (QPLL_CFG), .QPLL_FBDIV (QPLL_FBDIV)) i_xcm_12 ( .qpll_ref_clk (qpll_ref_clk_12), .qpll2ch_clk (qpll2ch_clk_12), .qpll2ch_ref_clk (qpll2ch_ref_clk_12), .qpll2ch_locked (qpll2ch_locked_12), .up_rstn (up_rstn), .up_clk (up_clk), .up_qpll_rst (up_qpll_rst_12), .up_cm_sel (up_cm_sel_12), .up_cm_enb (up_cm_enb_12), .up_cm_addr (up_cm_addr_12), .up_cm_wr (up_cm_wr_12), .up_cm_wdata (up_cm_wdata_12), .up_cm_rdata (up_cm_rdata_12), .up_cm_ready (up_cm_ready_12)); end endgenerate generate if (NUM_OF_LANES >= 13) begin util_adxcvr_xch #( .XCVR_ID (n), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE), .PMA_RSV (PMA_RSV), .RX_CDR_CFG (RX_CDR_CFG)) i_xch_12 ( .qpll2ch_clk (qpll2ch_clk_12), .qpll2ch_ref_clk (qpll2ch_ref_clk_12), .qpll2ch_locked (qpll2ch_locked_12), .cpll_ref_clk (cpll_ref_clk_12), .rx_p (rx_12_p), .rx_n (rx_12_n), .rx_out_clk (rx_out_clk_12), .rx_clk (rx_clk_12), .rx_charisk (rx_charisk_12), .rx_disperr (rx_disperr_12), .rx_notintable (rx_notintable_12), .rx_data (rx_data_12), .rx_calign (rx_calign_12), .tx_p (tx_12_p), .tx_n (tx_12_n), .tx_out_clk (tx_out_clk_12), .tx_clk (tx_clk_12), .tx_charisk (tx_charisk_12), .tx_data (tx_data_12), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_sel (up_es_sel_12), .up_es_enb (up_es_enb_12), .up_es_addr (up_es_addr_12), .up_es_wr (up_es_wr_12), .up_es_wdata (up_es_wdata_12), .up_es_rdata (up_es_rdata_12), .up_es_ready (up_es_ready_12), .up_rx_pll_rst (up_rx_pll_rst_12), .up_rx_pll_locked (up_rx_pll_locked_12), .up_rx_rst (up_rx_rst_12), .up_rx_user_ready (up_rx_user_ready_12), .up_rx_rst_done (up_rx_rst_done_12), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_12), .up_rx_rate (up_rx_rate_12), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_12), .up_rx_out_clk_sel (up_rx_out_clk_sel_12), .up_rx_sel (up_rx_sel_12), .up_rx_enb (up_rx_enb_12), .up_rx_addr (up_rx_addr_12), .up_rx_wr (up_rx_wr_12), .up_rx_wdata (up_rx_wdata_12), .up_rx_rdata (up_rx_rdata_12), .up_rx_ready (up_rx_ready_12), .up_tx_pll_rst (up_tx_pll_rst_12), .up_tx_pll_locked (up_tx_pll_locked_12), .up_tx_rst (up_tx_rst_12), .up_tx_user_ready (up_tx_user_ready_12), .up_tx_rst_done (up_tx_rst_done_12), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_12), .up_tx_rate (up_tx_rate_12), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_12), .up_tx_out_clk_sel (up_tx_out_clk_sel_12), .up_tx_sel (up_tx_sel_12), .up_tx_enb (up_tx_enb_12), .up_tx_addr (up_tx_addr_12), .up_tx_wr (up_tx_wr_12), .up_tx_wdata (up_tx_wdata_12), .up_tx_rdata (up_tx_rdata_12), .up_tx_ready (up_tx_ready_12)); end endgenerate generate if (NUM_OF_LANES >= 14) begin util_adxcvr_xch #( .XCVR_ID (n), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE), .PMA_RSV (PMA_RSV), .RX_CDR_CFG (RX_CDR_CFG)) i_xch_13 ( .qpll2ch_clk (qpll2ch_clk_12), .qpll2ch_ref_clk (qpll2ch_ref_clk_12), .qpll2ch_locked (qpll2ch_locked_12), .cpll_ref_clk (cpll_ref_clk_13), .rx_p (rx_13_p), .rx_n (rx_13_n), .rx_out_clk (rx_out_clk_13), .rx_clk (rx_clk_13), .rx_charisk (rx_charisk_13), .rx_disperr (rx_disperr_13), .rx_notintable (rx_notintable_13), .rx_data (rx_data_13), .rx_calign (rx_calign_13), .tx_p (tx_13_p), .tx_n (tx_13_n), .tx_out_clk (tx_out_clk_13), .tx_clk (tx_clk_13), .tx_charisk (tx_charisk_13), .tx_data (tx_data_13), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_sel (up_es_sel_13), .up_es_enb (up_es_enb_13), .up_es_addr (up_es_addr_13), .up_es_wr (up_es_wr_13), .up_es_wdata (up_es_wdata_13), .up_es_rdata (up_es_rdata_13), .up_es_ready (up_es_ready_13), .up_rx_pll_rst (up_rx_pll_rst_13), .up_rx_pll_locked (up_rx_pll_locked_13), .up_rx_rst (up_rx_rst_13), .up_rx_user_ready (up_rx_user_ready_13), .up_rx_rst_done (up_rx_rst_done_13), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_13), .up_rx_rate (up_rx_rate_13), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_13), .up_rx_out_clk_sel (up_rx_out_clk_sel_13), .up_rx_sel (up_rx_sel_13), .up_rx_enb (up_rx_enb_13), .up_rx_addr (up_rx_addr_13), .up_rx_wr (up_rx_wr_13), .up_rx_wdata (up_rx_wdata_13), .up_rx_rdata (up_rx_rdata_13), .up_rx_ready (up_rx_ready_13), .up_tx_pll_rst (up_tx_pll_rst_13), .up_tx_pll_locked (up_tx_pll_locked_13), .up_tx_rst (up_tx_rst_13), .up_tx_user_ready (up_tx_user_ready_13), .up_tx_rst_done (up_tx_rst_done_13), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_13), .up_tx_rate (up_tx_rate_13), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_13), .up_tx_out_clk_sel (up_tx_out_clk_sel_13), .up_tx_sel (up_tx_sel_13), .up_tx_enb (up_tx_enb_13), .up_tx_addr (up_tx_addr_13), .up_tx_wr (up_tx_wr_13), .up_tx_wdata (up_tx_wdata_13), .up_tx_rdata (up_tx_rdata_13), .up_tx_ready (up_tx_ready_13)); end endgenerate generate if (NUM_OF_LANES >= 15) begin util_adxcvr_xch #( .XCVR_ID (n), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE), .PMA_RSV (PMA_RSV), .RX_CDR_CFG (RX_CDR_CFG)) i_xch_14 ( .qpll2ch_clk (qpll2ch_clk_12), .qpll2ch_ref_clk (qpll2ch_ref_clk_12), .qpll2ch_locked (qpll2ch_locked_12), .cpll_ref_clk (cpll_ref_clk_14), .rx_p (rx_14_p), .rx_n (rx_14_n), .rx_out_clk (rx_out_clk_14), .rx_clk (rx_clk_14), .rx_charisk (rx_charisk_14), .rx_disperr (rx_disperr_14), .rx_notintable (rx_notintable_14), .rx_data (rx_data_14), .rx_calign (rx_calign_14), .tx_p (tx_14_p), .tx_n (tx_14_n), .tx_out_clk (tx_out_clk_14), .tx_clk (tx_clk_14), .tx_charisk (tx_charisk_14), .tx_data (tx_data_14), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_sel (up_es_sel_14), .up_es_enb (up_es_enb_14), .up_es_addr (up_es_addr_14), .up_es_wr (up_es_wr_14), .up_es_wdata (up_es_wdata_14), .up_es_rdata (up_es_rdata_14), .up_es_ready (up_es_ready_14), .up_rx_pll_rst (up_rx_pll_rst_14), .up_rx_pll_locked (up_rx_pll_locked_14), .up_rx_rst (up_rx_rst_14), .up_rx_user_ready (up_rx_user_ready_14), .up_rx_rst_done (up_rx_rst_done_14), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_14), .up_rx_rate (up_rx_rate_14), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_14), .up_rx_out_clk_sel (up_rx_out_clk_sel_14), .up_rx_sel (up_rx_sel_14), .up_rx_enb (up_rx_enb_14), .up_rx_addr (up_rx_addr_14), .up_rx_wr (up_rx_wr_14), .up_rx_wdata (up_rx_wdata_14), .up_rx_rdata (up_rx_rdata_14), .up_rx_ready (up_rx_ready_14), .up_tx_pll_rst (up_tx_pll_rst_14), .up_tx_pll_locked (up_tx_pll_locked_14), .up_tx_rst (up_tx_rst_14), .up_tx_user_ready (up_tx_user_ready_14), .up_tx_rst_done (up_tx_rst_done_14), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_14), .up_tx_rate (up_tx_rate_14), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_14), .up_tx_out_clk_sel (up_tx_out_clk_sel_14), .up_tx_sel (up_tx_sel_14), .up_tx_enb (up_tx_enb_14), .up_tx_addr (up_tx_addr_14), .up_tx_wr (up_tx_wr_14), .up_tx_wdata (up_tx_wdata_14), .up_tx_rdata (up_tx_rdata_14), .up_tx_ready (up_tx_ready_14)); end endgenerate generate if (NUM_OF_LANES >= 16) begin util_adxcvr_xch #( .XCVR_ID (n), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE), .PMA_RSV (PMA_RSV), .RX_CDR_CFG (RX_CDR_CFG)) i_xch_15 ( .qpll2ch_clk (qpll2ch_clk_12), .qpll2ch_ref_clk (qpll2ch_ref_clk_12), .qpll2ch_locked (qpll2ch_locked_12), .cpll_ref_clk (cpll_ref_clk_15), .rx_p (rx_15_p), .rx_n (rx_15_n), .rx_out_clk (rx_out_clk_15), .rx_clk (rx_clk_15), .rx_charisk (rx_charisk_15), .rx_disperr (rx_disperr_15), .rx_notintable (rx_notintable_15), .rx_data (rx_data_15), .rx_calign (rx_calign_15), .tx_p (tx_15_p), .tx_n (tx_15_n), .tx_out_clk (tx_out_clk_15), .tx_clk (tx_clk_15), .tx_charisk (tx_charisk_15), .tx_data (tx_data_15), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_sel (up_es_sel_15), .up_es_enb (up_es_enb_15), .up_es_addr (up_es_addr_15), .up_es_wr (up_es_wr_15), .up_es_wdata (up_es_wdata_15), .up_es_rdata (up_es_rdata_15), .up_es_ready (up_es_ready_15), .up_rx_pll_rst (up_rx_pll_rst_15), .up_rx_pll_locked (up_rx_pll_locked_15), .up_rx_rst (up_rx_rst_15), .up_rx_user_ready (up_rx_user_ready_15), .up_rx_rst_done (up_rx_rst_done_15), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_15), .up_rx_rate (up_rx_rate_15), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_15), .up_rx_out_clk_sel (up_rx_out_clk_sel_15), .up_rx_sel (up_rx_sel_15), .up_rx_enb (up_rx_enb_15), .up_rx_addr (up_rx_addr_15), .up_rx_wr (up_rx_wr_15), .up_rx_wdata (up_rx_wdata_15), .up_rx_rdata (up_rx_rdata_15), .up_rx_ready (up_rx_ready_15), .up_tx_pll_rst (up_tx_pll_rst_15), .up_tx_pll_locked (up_tx_pll_locked_15), .up_tx_rst (up_tx_rst_15), .up_tx_user_ready (up_tx_user_ready_15), .up_tx_rst_done (up_tx_rst_done_15), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_15), .up_tx_rate (up_tx_rate_15), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_15), .up_tx_out_clk_sel (up_tx_out_clk_sel_15), .up_tx_sel (up_tx_sel_15), .up_tx_enb (up_tx_enb_15), .up_tx_addr (up_tx_addr_15), .up_tx_wr (up_tx_wr_15), .up_tx_wdata (up_tx_wdata_15), .up_tx_rdata (up_tx_rdata_15), .up_tx_ready (up_tx_ready_15)); end endgenerate endmodule // *************************************************************************** // ***************************************************************************