####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################

LIBRARY_NAME := axi_ad9250

GENERIC_DEPS += axi_ad9250.v

XILINX_DEPS += axi_ad9250_ip.tcl

XILINX_LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc

ALTERA_DEPS += ../altera/common/up_clock_mon_constr.sdc
ALTERA_DEPS += ../altera/common/up_rst_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_cntrl_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_status_constr.sdc
ALTERA_DEPS += ../common/ad_datafmt.v
ALTERA_DEPS += ../common/ad_pnmon.v
ALTERA_DEPS += ../common/ad_rst.v
ALTERA_DEPS += ../common/ad_xcvr_rx_if.v
ALTERA_DEPS += ../common/up_adc_channel.v
ALTERA_DEPS += ../common/up_adc_common.v
ALTERA_DEPS += ../common/up_axi.v
ALTERA_DEPS += ../common/up_clock_mon.v
ALTERA_DEPS += ../common/up_xfer_cntrl.v
ALTERA_DEPS += ../common/up_xfer_status.v
ALTERA_DEPS += ../jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v
ALTERA_DEPS += ../jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v
ALTERA_DEPS += ../jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v
ALTERA_DEPS += ../jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v
ALTERA_DEPS += ../jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v
ALTERA_DEPS += ../jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v
ALTERA_DEPS += axi_ad9250_hw.tcl

include ../scripts/library.mk