// *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. // // All rights reserved. // // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // - Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in // the documentation and/or other materials provided with the // distribution. // - Neither the name of Analog Devices, Inc. nor the names of its // contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // - The use of this software may or may not infringe the patent rights // of one or more patent holders. This license does not release you // from the requirement that you obtain separate licenses from these // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. // // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY // RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** `timescale 1ns/100ps module system_top ( ddr_addr, ddr_ba, ddr_cas_n, ddr_ck_n, ddr_ck_p, ddr_cke, ddr_cs_n, ddr_dm, ddr_dq, ddr_dqs_n, ddr_dqs_p, ddr_odt, ddr_ras_n, ddr_reset_n, ddr_we_n, fixed_io_ddr_vrn, fixed_io_ddr_vrp, fixed_io_mio, fixed_io_ps_clk, fixed_io_ps_porb, fixed_io_ps_srstb, iic_scl, iic_sda, gpio_bd, rx_clk_in_p, rx_clk_in_n, rx_frame_in_p, rx_frame_in_n, rx_data_in_p, rx_data_in_n, tx_clk_out_p, tx_clk_out_n, tx_frame_out_p, tx_frame_out_n, tx_data_out_p, tx_data_out_n, enable, txnrx, gpio_clksel, gpio_resetb, gpio_sync, gpio_en_agc, gpio_ctl, gpio_status, spi_csn, spi_clk, spi_mosi, spi_miso, fmc_prstn, fmc_clk0_p, fmc_clk0_n, fmc_clk1_p, fmc_clk1_n, fmc_la_p, fmc_la_n, pmod0, pmod1, fmc_gt_ref_clk_p, fmc_gt_ref_clk_n, fmc_gt_tx_p, fmc_gt_tx_n, fmc_gt_rx_p, fmc_gt_rx_n); inout [14:0] ddr_addr; inout [ 2:0] ddr_ba; inout ddr_cas_n; inout ddr_ck_n; inout ddr_ck_p; inout ddr_cke; inout ddr_cs_n; inout [ 3:0] ddr_dm; inout [31:0] ddr_dq; inout [ 3:0] ddr_dqs_n; inout [ 3:0] ddr_dqs_p; inout ddr_odt; inout ddr_ras_n; inout ddr_reset_n; inout ddr_we_n; inout fixed_io_ddr_vrn; inout fixed_io_ddr_vrp; inout [53:0] fixed_io_mio; inout fixed_io_ps_clk; inout fixed_io_ps_porb; inout fixed_io_ps_srstb; inout iic_scl; inout iic_sda; inout [11:0] gpio_bd; input rx_clk_in_p; input rx_clk_in_n; input rx_frame_in_p; input rx_frame_in_n; input [ 5:0] rx_data_in_p; input [ 5:0] rx_data_in_n; output tx_clk_out_p; output tx_clk_out_n; output tx_frame_out_p; output tx_frame_out_n; output [ 5:0] tx_data_out_p; output [ 5:0] tx_data_out_n; output enable; output txnrx; inout gpio_clksel; inout gpio_resetb; inout gpio_sync; inout gpio_en_agc; inout [ 3:0] gpio_ctl; inout [ 7:0] gpio_status; output spi_csn; output spi_clk; output spi_mosi; input spi_miso; input fmc_prstn; input fmc_clk0_p; input fmc_clk0_n; input fmc_clk1_p; input fmc_clk1_n; inout [33:0] fmc_la_p; inout [33:0] fmc_la_n; inout [ 7:0] pmod0; inout [ 7:0] pmod1; input fmc_gt_ref_clk_p; input fmc_gt_ref_clk_n; output fmc_gt_tx_p; output fmc_gt_tx_n; input fmc_gt_rx_p; input fmc_gt_rx_n; // internal signals wire fmc_clk0_s; wire fmc_clk0; wire [31:0] up_clk0_count; wire fmc_clk1_s; wire fmc_clk1; wire [31:0] up_clk1_count; wire fmc_gt_ref_clk; wire [31:0] gpio_0_0_i; wire [31:0] gpio_0_0_o; wire [31:0] gpio_0_0_t; wire [31:0] gpio_0_1_i; wire [31:0] gpio_0_1_o; wire [31:0] gpio_0_1_t; wire [31:0] gpio_1_0_i; wire [31:0] gpio_1_0_o; wire [31:0] gpio_1_0_t; wire [31:0] gpio_1_1_i; wire [31:0] gpio_1_1_o; wire [31:0] gpio_1_1_t; wire [31:0] gpio_3_1_o; wire [63:0] gpio_i; wire [63:0] gpio_o; wire [63:0] gpio_t; wire up_clk; wire up_rst; wire up_rstn; wire up_pn_err_clr; wire up_pn_oos_clr; wire up_pn_err; wire up_pn_oos; // instantiations IBUFDS i_ibufds_clk0 ( .I (fmc_clk0_p), .IB (fmc_clk0_n), .O (fmc_clk0_s)); BUFG i_bufg_clk0 ( .I (fmc_clk0_s), .O (fmc_clk0)); up_clock_mon i_clk0_mon ( .up_rstn (up_rstn), .up_clk (up_clk), .up_d_count (up_clk0_count), .d_rst (up_rst), .d_clk (fmc_clk0)); IBUFDS i_ibufds_clk1 ( .I (fmc_clk1_p), .IB (fmc_clk1_n), .O (fmc_clk1_s)); BUFG i_bufg_clk1 ( .I (fmc_clk1_s), .O (fmc_clk1)); up_clock_mon i_clk1_mon ( .up_rstn (up_rstn), .up_clk (up_clk), .up_d_count (up_clk1_count), .d_rst (up_rst), .d_clk (fmc_clk1)); IBUFDS_GTE2 i_ibufds_ref_clk ( .CEB (1'd0), .I (fmc_gt_ref_clk_p), .IB (fmc_gt_ref_clk_n), .O (fmc_gt_ref_clk), .ODIV2 ()); assign gpio_0_1_i[31:10] = 'd0; assign gpio_1_1_i[31:10] = 'd0; assign up_pn_err_clr = gpio_3_1_o[1]; assign up_pn_oos_clr = gpio_3_1_o[0]; ad_iobuf #(.DATA_WIDTH(42)) i_iobuf_pmod0_fmc_p ( .dio_t ({gpio_0_1_t[9:0], gpio_0_0_t[31:0]}), .dio_i ({gpio_0_1_o[9:0], gpio_0_0_o[31:0]}), .dio_o ({gpio_0_1_i[9:0], gpio_0_0_i[31:0]}), .dio_p ({ pmod1[3], pmod1[2], pmod1[1], pmod1[0], pmod0[3], pmod0[2], pmod0[1], pmod0[0], fmc_la_n[16:0], fmc_la_p[16:0]})); ad_iobuf #(.DATA_WIDTH(42)) i_iobuf_pmod1_fmc_n ( .dio_t ({gpio_1_1_t[9:0], gpio_1_0_t[31:0]}), .dio_i ({gpio_1_1_o[9:0], gpio_1_0_o[31:0]}), .dio_o ({gpio_1_1_i[9:0], gpio_1_0_i[31:0]}), .dio_p ({ pmod1[7], pmod1[6], pmod1[5], pmod1[4], pmod0[7], pmod0[6], pmod0[5], pmod0[4], fmc_la_n[33:17], fmc_la_p[33:17]})); ad_iobuf #(.DATA_WIDTH(16)) i_iobuf ( .dio_t ({gpio_t[51], gpio_t[46:32]}), .dio_i ({gpio_o[51], gpio_o[46:32]}), .dio_o ({gpio_i[51], gpio_i[46:32]}), .dio_p ({ gpio_clksel, // 51:51 gpio_resetb, // 46:46 gpio_sync, // 45:45 gpio_en_agc, // 44:44 gpio_ctl, // 43:40 gpio_status})); // 39:32 ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd ( .dio_t (gpio_t[11:0]), .dio_i (gpio_o[11:0]), .dio_o (gpio_i[11:0]), .dio_p (gpio_bd)); system_wrapper i_system_wrapper ( .ddr_addr (ddr_addr), .ddr_ba (ddr_ba), .ddr_cas_n (ddr_cas_n), .ddr_ck_n (ddr_ck_n), .ddr_ck_p (ddr_ck_p), .ddr_cke (ddr_cke), .ddr_cs_n (ddr_cs_n), .ddr_dm (ddr_dm), .ddr_dq (ddr_dq), .ddr_dqs_n (ddr_dqs_n), .ddr_dqs_p (ddr_dqs_p), .ddr_odt (ddr_odt), .ddr_ras_n (ddr_ras_n), .ddr_reset_n (ddr_reset_n), .ddr_we_n (ddr_we_n), .enable (enable), .fixed_io_ddr_vrn (fixed_io_ddr_vrn), .fixed_io_ddr_vrp (fixed_io_ddr_vrp), .fixed_io_mio (fixed_io_mio), .fixed_io_ps_clk (fixed_io_ps_clk), .fixed_io_ps_porb (fixed_io_ps_porb), .fixed_io_ps_srstb (fixed_io_ps_srstb), .fmc_gt_ref_clk0 (fmc_gt_ref_clk), .fmc_gt_ref_clk1 (fmc_gt_ref_clk), .fmc_gt_rx_n (fmc_gt_rx_n), .fmc_gt_rx_p (fmc_gt_rx_p), .fmc_gt_tx_n (fmc_gt_tx_n), .fmc_gt_tx_p (fmc_gt_tx_p), .gpio_0_0_i (gpio_0_0_i), .gpio_0_0_o (gpio_0_0_o), .gpio_0_0_t (gpio_0_0_t), .gpio_0_1_i (gpio_0_1_i), .gpio_0_1_o (gpio_0_1_o), .gpio_0_1_t (gpio_0_1_t), .gpio_1_0_i (gpio_1_0_i), .gpio_1_0_o (gpio_1_0_o), .gpio_1_0_t (gpio_1_0_t), .gpio_1_1_i (gpio_1_1_i), .gpio_1_1_o (gpio_1_1_o), .gpio_1_1_t (gpio_1_1_t), .gpio_2_0_i (up_clk0_count), .gpio_2_0_o (), .gpio_2_0_t (), .gpio_2_1_i (up_clk1_count), .gpio_2_1_o (), .gpio_2_1_t (), .gpio_3_0_i ({31'd0, fmc_prstn}), .gpio_3_0_o (), .gpio_3_0_t (), .gpio_3_1_i ({30'd0, up_pn_err, up_pn_oos}), .gpio_3_1_o (gpio_3_1_o), .gpio_3_1_t (), .gpio_i (gpio_i), .gpio_o (gpio_o), .gpio_t (gpio_t), .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), .otg_vbusoc (1'b0), .ps_intr_00 (1'b0), .ps_intr_01 (1'b0), .ps_intr_02 (1'b0), .ps_intr_03 (1'b0), .ps_intr_04 (1'b0), .ps_intr_05 (1'b0), .ps_intr_06 (1'b0), .ps_intr_07 (1'b0), .ps_intr_08 (1'b0), .ps_intr_09 (1'b0), .ps_intr_10 (1'b0), .ps_intr_11 (1'b0), .ps_intr_15 (1'b0), .rx_clk_in_n (rx_clk_in_n), .rx_clk_in_p (rx_clk_in_p), .rx_data_in_n (rx_data_in_n), .rx_data_in_p (rx_data_in_p), .rx_frame_in_n (rx_frame_in_n), .rx_frame_in_p (rx_frame_in_p), .spi0_clk_i (1'b0), .spi0_clk_o (spi_clk), .spi0_csn_0_o (spi_csn), .spi0_csn_1_o (), .spi0_csn_2_o (), .spi0_csn_i (1'b1), .spi0_sdi_i (spi_miso), .spi0_sdo_i (1'b0), .spi0_sdo_o (spi_mosi), .spi1_clk_i (1'b0), .spi1_clk_o (), .spi1_csn_0_o (), .spi1_csn_1_o (), .spi1_csn_2_o (), .spi1_csn_i (1'b1), .spi1_sdi_i (1'b0), .spi1_sdo_i (1'b0), .spi1_sdo_o (), .tdd_sync_i (1'b0), .tdd_sync_o (), .tdd_sync_t (), .tx_clk_out_n (tx_clk_out_n), .tx_clk_out_p (tx_clk_out_p), .tx_data_out_n (tx_data_out_n), .tx_data_out_p (tx_data_out_p), .tx_frame_out_n (tx_frame_out_n), .tx_frame_out_p (tx_frame_out_p), .txnrx (txnrx), .up_clk (up_clk), .up_enable (gpio_o[47]), .up_pn_err (up_pn_err), .up_pn_err_clr (up_pn_err_clr), .up_pn_oos (up_pn_oos), .up_pn_oos_clr (up_pn_oos_clr), .up_rst (up_rst), .up_rstn (up_rstn), .up_txnrx (gpio_o[48])); endmodule // *************************************************************************** // ***************************************************************************