// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
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// data format (offset binary or 2's complement only)

`timescale 1ps/1ps

module ad_datafmt (

  // data path

  clk,
  valid,
  data,
  valid_out,
  data_out,

  // control signals

  dfmt_enable,
  dfmt_type,
  dfmt_se);

  // delayed data bus width

  parameter   DATA_WIDTH = 16;
  parameter   DATA_WIDTH_OUT = 16;
  localparam  DW = DATA_WIDTH - 1;
  localparam  DW1 = DATA_WIDTH_OUT - 1;

  // data path

  input            clk;
  input            valid;
  input   [ DW:0]  data;
  output           valid_out;
  output  [DW1:0]  data_out;

  // control signals

  input           dfmt_enable;
  input           dfmt_type;
  input           dfmt_se;

  // internal registers

  reg              valid_out = 'd0;
  reg     [DW1:0]  data_out = 'd0;

  // internal signals

  wire             type_s;
  wire             signext_s;
  wire    [ DW:0]  data_s;
  wire    [DW1:0]  sign_s;
  wire    [DW1:0]  data_out_s;

  // if offset-binary convert to 2's complement first

  assign type_s = dfmt_enable & dfmt_type;
  assign signext_s = dfmt_enable & dfmt_se;

  assign data_s = (type_s == 1'b1) ? {~data[DW], data[(DW-1):0]} : data;
  assign sign_s = (signext_s == 1'b1) ? {{DW1{data_s[DW]}}} : 0;
  
  generate
  if (DW == DW1) begin
	assign data_out_s = data_s;
  end else begin
	assign data_out_s = {sign_s[DW1:(DW+1)], data_s};
  end
  endgenerate 

  always @(posedge clk) begin
    valid_out <= valid;
    data_out  <= valid ? data_out_s[DW1:0] : data_out;
  end

endmodule

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