create_clock -period "10.000 ns"  -name sys_clk_100mhz        [get_ports {sys_clk}]
create_clock -period "4.000 ns"   -name ref_clk_250mhz        [get_ports {ref_clk}]
create_clock -period "8.000 ns"   -name eth_rx_clk_125mhz     [get_ports {eth_rx_clk}]

derive_pll_clocks
derive_clock_uncertainty

set_clock_groups -exclusive \
  -group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
  -group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \
  -group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] \

set_false_path -from [get_registers *dev_sync_n*] -to [get_registers *rx_sync_m1*]
set_false_path -from [get_registers *rx_sysref*]  -to [get_registers *sys_xcvr*sysref*]