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`timescale 1ns/1ns

module prcfg_adc (
  clk,

  // control ports
  control,
  status,

  // FIFO interface
  src_adc_dwr,
  src_adc_dsync,
  src_adc_ddata,
  src_adc_dovf,

  dst_adc_dwr,
  dst_adc_dsync,
  dst_adc_ddata,
  dst_adc_dovf
);

  localparam  RP_ID       = 8'hA1;
  parameter   CHANNEL_ID  = 0;

  input             clk;

  input   [31:0]    control;
  output  [31:0]    status;

  input             src_adc_dwr;
  input             src_adc_dsync;
  input   [31:0]    src_adc_ddata;
  output            src_adc_dovf;

  output            dst_adc_dwr;
  output            dst_adc_dsync;
  output  [31:0]    dst_adc_ddata;
  input             dst_adc_dovf;

  reg               dst_adc_dwr;
  reg               dst_adc_dsync;
  reg     [31:0]    dst_adc_ddata;
  reg               src_adc_dovf;

  reg     [31:0]    status            = 0;
  reg     [31:0]    adc_pn_data       = 0;

  reg     [ 3:0]    mode;
  reg     [ 3:0]    channel_sel;

  wire              adc_dvalid;
  wire    [31:0]    adc_pn_data_s;
  wire              adc_pn_oos_s;
  wire              adc_pn_err_s;


  // prbs function

  function [31:0] pn;
    input [31:0] din;
    reg   [31:0] dout;
    begin
      dout[31]  = din[14] ^ din[13];
      dout[30]  = din[13] ^ din[12];
      dout[29]  = din[12] ^ din[11];
      dout[28]  = din[11] ^ din[10];
      dout[27]  = din[10] ^ din[9];
      dout[26]  = din[9]  ^ din[8];
      dout[25]  = din[8]  ^ din[7];
      dout[24]  = din[7]  ^ din[6];
      dout[23]  = din[6]  ^ din[5];
      dout[22]  = din[5]  ^ din[4];
      dout[21]  = din[4]  ^ din[3];
      dout[20]  = din[3]  ^ din[2];
      dout[19]  = din[2]  ^ din[1];
      dout[18]  = din[1]  ^ din[0];
      dout[17]  = din[0]  ^ din[14] ^ din[13];
      dout[16]  = din[14] ^ din[12];
      dout[15]  = din[13] ^ din[11];
      dout[14]  = din[12] ^ din[10];
      dout[13]  = din[11] ^ din[9];
      dout[12]  = din[10] ^ din[8];
      dout[11]  = din[9]  ^ din[7];
      dout[10]  = din[8]  ^ din[6];
      dout[9]   = din[7]  ^ din[5];
      dout[8]   = din[6]  ^ din[4];
      dout[7]   = din[5]  ^ din[3];
      dout[6]   = din[4]  ^ din[2];
      dout[5]   = din[3]  ^ din[1];
      dout[4]   = din[2]  ^ din[0];
      dout[3]   = din[1]  ^ din[14] ^ din[13];
      dout[2]   = din[0]  ^ din[13] ^ din[12];
      dout[1]   = din[14] ^ din[12] ^ din[13] ^ din[11];
      dout[0]   = din[13] ^ din[11] ^ din[12] ^ din[10];
      pn = dout;
    end
  endfunction

  assign adc_dvalid = src_adc_dwr & src_adc_dsync;

  always @(posedge clk) begin
    channel_sel  <= control[3:0];
    mode         <= control[7:4];
  end

  // prbs generation
  always @(posedge clk) begin
    if(adc_dvalid == 1'b1) begin
      adc_pn_data <= pn(adc_pn_data_s);
    end
  end

  assign adc_pn_data_s = (adc_pn_oos_s == 1'b1) ? src_adc_ddata : adc_pn_data;

  ad_pnmon #(
    .DATA_WIDTH(32)
  ) i_pn_mon (
    .adc_clk(clk),
    .adc_valid_in(adc_dvalid),
    .adc_data_in(src_adc_ddata),
    .adc_data_pn(adc_pn_data),
    .adc_pn_oos(adc_pn_oos_s),
    .adc_pn_err(adc_pn_err_s));

  // rx path are passed through on test mode
  always @(posedge clk) begin
    dst_adc_dwr    <= src_adc_dwr;
    dst_adc_dsync  <= src_adc_dsync;
    dst_adc_ddata  <= src_adc_ddata;
    src_adc_dovf   <= dst_adc_dovf;
  end

  // setup status bits for gpio_out
  always @(posedge clk) begin
    if((mode == 3'd2) && (channel_sel == CHANNEL_ID)) begin
      status <= {22'h0, adc_pn_err_s, adc_pn_oos_s, RP_ID};
    end else begin
      status <= {24'h0, RP_ID};
    end
  end

endmodule