// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
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// ***************************************************************************
// ***************************************************************************

`timescale 1ns/100ps

module util_jesd_align (

  // xcvr interface

  rx_clk,
  rx_ip_sof,
  rx_ip_data,
  rx_sof,
  rx_data,

  rx_st_valid,
  rx_st_data);

  // parameters

  parameter   NUM_OF_LANES = 2;
  parameter   ST_VALID_WIDTH = 1;
  parameter   ST_DATA_WIDTH = 128;

  // xcvr interface

  input                               rx_clk;
  input   [ 3:0]                      rx_ip_sof;
  input   [((NUM_OF_LANES*32)-1):0]   rx_ip_data;
  output  [((NUM_OF_LANES* 1)-1):0]   rx_sof;
  output  [((NUM_OF_LANES*32)-1):0]   rx_data;

  output  [(ST_VALID_WIDTH-1):0]      rx_st_valid;
  output  [(ST_DATA_WIDTH-1):0]       rx_st_data;

  // internal signals

  wire    [((NUM_OF_LANES*64)+3):0]   rx_st_data_s;

  // only for altera, xcvr+jesd do not frame align

  assign rx_st_data_s = {rx_ip_sof, rx_ip_data, rx_data};
  assign rx_st_data = rx_st_data_s[(ST_DATA_WIDTH-1):0];
  assign rx_st_valid = 'd1;

  genvar n;
  generate
  for (n = 0; n < NUM_OF_LANES; n = n + 1) begin: g_lane
  ad_jesd_align i_jesd_align (
    .rx_clk (rx_clk),
    .rx_ip_sof (rx_ip_sof),
    .rx_ip_data (rx_ip_data[n*32+31:n*32]),
    .rx_sof (rx_sof[n]),
    .rx_data (rx_data[n*32+31:n*32]));
  end
  endgenerate

endmodule

// ***************************************************************************
// ***************************************************************************