// ***************************************************************************
// ***************************************************************************
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// ***************************************************************************
// ***************************************************************************

`timescale 1ns/100ps

module ad_jesd_align (

  // jesd interface

  rx_clk,
  rx_sof,
  rx_ip_data,
  rx_data);

  // jesd interface

  input           rx_clk;
  input   [ 3:0]  rx_sof;
  input   [31:0]  rx_ip_data;

  // aligned data

  output  [31:0]  rx_data;

  // internal registers

  reg     [31:0]  rx_ip_data_d = 'd0;
  reg     [31:0]  rx_data = 'd0;

  // dword may contain more than one frame per clock

  always @(posedge rx_clk) begin
    rx_ip_data_d <= rx_ip_data;
    if (rx_sof[3] == 1'b1) begin
      rx_data[31:24] <= rx_ip_data[ 7: 0];
      rx_data[23:16] <= rx_ip_data[15: 8];
      rx_data[15: 8] <= rx_ip_data[23:16];
      rx_data[ 7: 0] <= rx_ip_data[31:24];
    end else if (rx_sof[2] == 1'b1) begin
      rx_data[31:24] <= rx_ip_data[31:24];
      rx_data[23:16] <= rx_ip_data_d[ 7: 0];
      rx_data[15: 8] <= rx_ip_data_d[15: 8];
      rx_data[ 7: 0] <= rx_ip_data_d[23:16];
    end else if (rx_sof[1] == 1'b1) begin
      rx_data[31:24] <= rx_ip_data[23:16];
      rx_data[23:16] <= rx_ip_data[31:24];
      rx_data[15: 8] <= rx_ip_data_d[ 7: 0];
      rx_data[ 7: 0] <= rx_ip_data_d[15: 8];
    end else if (rx_sof[0] == 1'b1) begin
      rx_data[31:24] <= rx_ip_data[15: 8];
      rx_data[23:16] <= rx_ip_data[23:16];
      rx_data[15: 8] <= rx_ip_data[31:24];
      rx_data[ 7: 0] <= rx_ip_data_d[ 7: 0];
    end else begin
      rx_data[31:24] <= 8'd0;
      rx_data[23:16] <= 8'd0;
      rx_data[15: 8] <= 8'd0;
      rx_data[ 7: 0] <= 8'd0;
    end
  end

endmodule

// ***************************************************************************
// ***************************************************************************