############################################################################### ## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. # SPDX short identifier: ADIBSD ############################################################################### <: :> <: set ComponentName [getComponentNameString] :> <: setOutputDirectory "./sim/" :> <: setFileName ${ComponentName}_pkg :> <: setFileExtension ".sv" :> <: set id [get_property MODELPARAM_VALUE.ID] :> <: set mem_type [get_property MODELPARAM_VALUE.MEM_TYPE] :> <: set mem_size_log2 [get_property MODELPARAM_VALUE.MEM_SIZE_LOG2] :> <: set tx_or_rxn_path [get_property MODELPARAM_VALUE.TX_OR_RXN_PATH] :> <: set src_data_width [get_property MODELPARAM_VALUE.src_data_width] :> <: set dst_data_width [get_property MODELPARAM_VALUE.dst_data_width] :> <: set dst_cyclic_en [get_property MODELPARAM_VALUE.dst_cyclic_en] :> // boolean to intiger <: proc b2i {b} { if {$b==true} {return 1} else {return 0}} :> // C hex to verilog hex <: proc h2vh {a} { return [string replace $a 0 1 "'h"]} :> /////////////////////////////////////////////////////////////////////////// //NOTE: This file has been automatically generated by Vivado. /////////////////////////////////////////////////////////////////////////// package <=: ComponentName :>_pkg; /////////////////////////////////////////////////////////////////////////// // These parameters are named after the component for use in your verification // environment. /////////////////////////////////////////////////////////////////////////// parameter <=: ComponentName :>_ID = <=: $id :>; parameter <=: ComponentName :>_MEM_TYPE = <=: $mem_type :>; parameter <=: ComponentName :>_MEM_SIZE_LOG2 = <=: $mem_size_log2 :>; parameter <=: ComponentName :>_TX_OR_RXN_PATH = <=: b2i $tx_or_rxn_path :>; parameter <=: ComponentName :>_SRC_DATA_WIDTH = <=: b2i $src_data_width :>; parameter <=: ComponentName :>_DST_DATA_WIDTH = <=: b2i $dst_data_width :>; parameter <=: ComponentName :>_DST_CYCLIC_EN = <=: b2i $dst_cyclic_en :>; ////////////////////////////////////////////////////////////////////////// endpackage : <=: ComponentName :>_pkg