.. _spi_engine:

SPI Engine
================================================================================

.. toctree::
   :hidden:

   Execution Module<spi_engine_execution>
   AXI Module<axi_spi_engine>
   Offload Module<spi_engine_offload>
   Interconnect Module<spi_engine_interconnect>
   Control Interface<control-interface>
   Offload Control Interface<offload-control-interface>
   SPI Bus Interface<spi-bus-interface>
   Instruction Set Specification<instruction-format>
   Pipeline Delays<pipeline-delays>
   Tutorial - PulSAR ADC<tutorial>
   

SPI Engine is a highly flexible and powerful SPI controller framework.
It consist out of multiple sub-modules which communicate over well defined
interfaces.
This allows a high degree of flexibility and re-usability while at the same time
staying highly customizable and easily extensible.

The core component of the SPI Engine framework is a lean but powerful fully
programmable execution module, which implements the SPI bus control logic.
The SPI Engine execution module is controlled by a command stream which is
generated by a separate module. Different command stream master modules are
available and can be used depending on the system requirements.
For example a software controlled memory mapped command stream offers high
flexibility, while a offload core which executes a pre-programmed command stream
when triggered by an external event allows for very low latency response times.
By using a SPI Engine interconnect it is possible to connect multiple command
stream master modules to a SPI Engine execution module.

Sub-modules
--------------------------------------------------------------------------------

* :ref:`spi_engine execution`: Main module which processes a SPI engine command
  stream and implements the SPI bus interface logic.
* :ref:`spi_engine axi`: Memory mapped software accessible interface to a
  SPI Engine command stream and/or offload cores.
* :ref:`spi_engine offload`: Stores a SPI Engine command stream, execution is
  triggered by an external event.
* :ref:`spi_engine interconnect`: Connects multiple SPI Engine command streams
  to a SPI Engine execution module.

Interfaces
--------------------------------------------------------------------------------

* :ref:`spi_engine control-interface`: SPI Engine command stream.
* :ref:`spi_engine offload-control-interface`: Program the command stream stored
  in a offload module.
* :ref:`spi_engine spi-bus-interface`: Low-level SPI bus interface.

Software
--------------------------------------------------------------------------------

* :dokuwiki:`Linux Driver <resources/tools-software/linux-drivers/spi/spi_engine>`:
  Linux driver for the SPI Engine framework.
* :ref:`spi_engine instruction-format`: Overview of the SPI Engine Instruction
  format.

Related IP Cores
--------------------------------------------------------------------------------

This list contains cores that are not part of the core SPI engine framework but
make use of its interfaces and are intended to be used together with the SPI engine
framework.

* :dokuwiki:`util-sigma-delta-spi <resources/fpga/peripherals/util_sigma_delta_spi>`:
  Helper module for interfacing ADCs from the Analog Devices Sigma-Delta family.

Examples
--------------------------------------------------------------------------------

* :dokuwiki:`CN0363 <resources/eval/user-guides/eval-cn0363-pmdz>`:
  Colorimeter application using the :adi:`AD7175-2` Sigma-Delta ADC.
* :dokuwiki:`resources/eval/user-guides/adaq7980-sdz`:
  A 16-bit ADC subsystem with four common signal processing and conditioning blocks.
* :dokuwiki:`resources/tools-software/uc-drivers/ad5766`:
  16-channel, 16-/12-bit, voltage output Digital-to-Analog Converters (DAC).
* :dokuwiki:`CN0363 <resources/eval/user-guides/eval-cn0363-pmdz>`:
  The AD7768-1 is a low power, high performance, Σ-Δ analog-to-digital converter (ADC).
* :git-hdl:`projects/ad40xx_fmc`
  Evaluation Board for the AD4000 Series 16-/18-/20-Bit Precision SAR ADCs.
* :dokuwiki:`AD469x <resources/eval/user-guides/ad469x>`:
  16-Bit, 16-Channel, 500 kSPS/1 MSPS, Easy Drive Multiplexed SAR ADC.
* :dokuwiki:`AD4630-24 / AD4030-24 / AD4630-16 <resources/eval/user-guides/ad463x/hdl>`:
  16/24-Bit, 2 MSPS Single or Dual Channel SAR ADC.

Additional Resources
--------------------------------------------------------------------------------

* :download:`Presentation: SPI Engine Design Philosophy <https://wiki.analog.com/_media/resources/fpga/peripherals/spi-engine3.pdf>`.
* :ref:`spi_engine pipeline-delays`
* :ref:`spi_engine tutorial`.