// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
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// are permitted provided that the following conditions are met:
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// ***************************************************************************
// This IP allows the interpolation by 8 of the data from the input
// The interpolation filter is implemented using a fir_compiler IP from
// Xilinx.
// ***************************************************************************

`timescale 1ns/100ps

module util_fir_int (
  input               aclk,
  input               s_axis_data_tvalid,
  output              s_axis_data_tready,
  input       [31:0]  s_axis_data_tdata,
  output      [15:0]  channel_0,
  output      [15:0]  channel_1,
  output              m_axis_data_tvalid,
  input               interpolate,
  input               dac_read);

  wire [31:0] m_axis_data_tdata_s;

  reg         s_axis_data_tready_r;
  reg   [2:0] ready_counter;

  always @(posedge aclk) begin
    ready_counter <= ready_counter + 1;
    if (ready_counter == 0) begin
      s_axis_data_tready_r <= 1'b1;
    end else begin
      s_axis_data_tready_r <= 1'b0;
    end
  end

  assign {channel_1, channel_0} = (interpolate == 1'b1) ? m_axis_data_tdata_s : s_axis_data_tdata;
  assign s_axis_data_tready = (interpolate == 1'b1) ? s_axis_data_tready_r : dac_read;

  fir_interp interpolator (
    .aclk(aclk),
    .s_axis_data_tvalid(s_axis_data_tvalid),
    .s_axis_data_tready(),
    .s_axis_data_tdata(s_axis_data_tdata),
    .m_axis_data_tvalid(m_axis_data_tvalid),
    .m_axis_data_tdata(m_axis_data_tdata_s)
  );

endmodule  // util_fir_int