212 lines
7.5 KiB
ReStructuredText
212 lines
7.5 KiB
ReStructuredText
.. _axi_hdmi_tx:
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AXI HDMI TX
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===============================================================================
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.. hdl-component-diagram::
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The :git-hdl:`AXI HDMI TX <library/axi_hdmi_tx>` IP core can be used to interface
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the :adi:`ADV7511` and :adi:`ADV7123` devices using an FPGA.
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Features
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-------------------------------------------------------------------------------
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* AXI based configuration
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* Supports multiple resolution (max 1080p)
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* Video transmission on 36/24/16 bits or 8 bits RGB
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* Supports embedded sync (16bit data)
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* YCbCr or RGB color space output
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* Data clipping (min. and max. for each chroma/color value)
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* Supports Xilinx 7 Series and Ultrascale devices.
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* Supports Altera 5 Series SoC
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Files
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--------------------------------------------------------------------------------
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.. list-table::
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:header-rows: 1
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* - Name
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- Description
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* - :git-hdl:`library/axi_hdmi_tx/axi_hdmi_tx.v`
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- Verilog source for the peripheral.
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.. _axi_hdmi_tx block-diagram:
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Block Diagram
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--------------------------------------------------------------------------------
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.. image:: block_diagram.svg
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:alt: AXI HDMI TX block diagram
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:align: center
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Configuration Parameters
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-------------------------------------------------------------------------------
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.. hdl-parameters::
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* - ID
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- Core ID should be unique for each axi_hdmi_tx IP in the system.
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* - FPGA_TECHNOLOGY
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- Used to select the FPGA Technolgy; beyond the "Choices/Range" listed, also
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supports Altera 5 series (101) devices.
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* - CR_CB_N
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- | Used in the chroma subsampling process, selecting which of the red or blue
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| data components will be transmitted first in-between green samples. 1 = red, 0 = blue
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* - INTERFACE
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- | Interface type towards the 7511. Available options: 16_BIT, 24_BIT, 36_BIT,
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| 16_BIT_EMBEDDED_SYNC, VGA_INTERFACE
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* - OUT_CLK_POLARITY
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- 0 = Launch on rising edge, 1 = Launch on falling edge.
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Interfaces
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-------------------------------------------------------------------------------
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.. hdl-interfaces::
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* - reference_clk
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- Pixel clock, generated by an axi_clkgen IP core (axi_hdmi_clkgen in
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reference design.
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* - hdmi_out_clk
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- Output clock.
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* - s_axis
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- DMA AXIS interface (vdma).
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* - hdmi_16_hsync
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- Horizontal sync signal.
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* - hdmi_16_vsync
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- Vertical sync signal.
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* - hdmi_16_data_e
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- Data enable signal.
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* - hdmi_16_data
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- HDMI data.
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* - hdmi_16_es_data
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- HDMI embedded sync data.
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* - hdmi_24_hsync
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- Horizontal sync signal.
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* - hdmi_24_vsync
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- Vertical sync signal.
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* - hdmi_24_data_e
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- Data enable signal.
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* - hdmi_24_data
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- HDMI data.
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* - hdmi_36_hsync
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- Horizontal sync signal.
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* - hdmi_36_vsync
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- Vertical sync signal.
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* - hdmi_36_data_e
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- Data enable signal.
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* - hdmi_36_data
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- HDMI data.
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* - vga_out_clk
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- Output clock.
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* - vga_hsync
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- Horizontal sync signal.
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* - vga_vsync
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- Vertical sync signal.
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* - vga_red
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- VGA red data.
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* - vga_green
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- VGA green data.
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* - vga_blue
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- VGA red data.
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Detailed description
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-------------------------------------------------------------------------------
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The top module (**axi_hdmi_tx**), instantiates:
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* axi_hdmi_tx_core module
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* axi_hdmi_tx_vdma module
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* the HDMI TX register map
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* the AXI handling interface
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In **axi_hdmi_tx_core** module the video information is manipulated by passing
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through several processing blocks (see :ref:`axi_hdmi_tx block-diagram`):
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* **CSC (Color Space Converter)** –converts the video information from RGB color
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space to YCbCr color space. If RGB is the desired output color space the CSC
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block can be bypassed by setting to 1 the value of CSC_BYPASS register.
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* **Data Clipping** bloc gives the possibility of limiting the minimum and
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maximum color range values. This block is controlled by FULL_RANGE, CLIPP_MAX
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and CLIPP_MIN registers.
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* **Chroma subsampling** block as its name suggests, samples the video
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information to obtain a video information that requires less bandwidth and
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has a minimum impact on the video quality experienced by human eyes.
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* **Embedded Sync** module interleaves the video synchronization signals with
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the video information, obtaining a more compact transmission path.
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* **Sync Signals** block is responsible for generating the video synchronization
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signals for video resolutions written in HDMI interface Control register.
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The **axi_hdmi_tx_vdma** module ensures the clock domain crossing circuit
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between the video source, typically a :ref:`axi_dmac` core and the
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**axi_hdmi_core**, which works at different clock speeds depending on the
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required resolution.
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Register Map
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-------------------------------------------------------------------------------
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.. hdl-regmap::
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:name: HDMI_TX
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Design considerations
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-------------------------------------------------------------------------------
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Additional IPs needed:
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* :ref:`axi_dmac`
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* :ref:`axi_clkgen`
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* :git-hdl:`library/axi_spdif_tx`
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:ref:`axi_dmac` provides a high-bandwidth direct memory access for the video stream.
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The core is configured as follows:
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.. code:: tcl
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ad_ip_instance axi_dmac axi_hdmi_dma
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ad_ip_parameter axi_hdmi_dma CONFIG.DMA_TYPE_SRC 0
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ad_ip_parameter axi_hdmi_dma CONFIG.DMA_TYPE_DEST 1
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ad_ip_parameter axi_hdmi_dma CONFIG.CYCLIC true
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ad_ip_parameter axi_hdmi_dma CONFIG.DMA_2D_TRANSFER true
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ad_ip_parameter axi_hdmi_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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The audio path is separated from the video path, for audio **axi_spdif_tx** core
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(:git-hdl:`axi_spdif_tx <library/axi_spdif_tx>`) is needed to transmit the audio
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information to the ADV7511 device.
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The whole system needs to be controlled by a processor (ARM or a soft core) that
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can programs the registers.
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``axi_clkgen`` generates the clock frequency required for the desired resolution
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(pixel clock), the frequency is software configurable
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(:git-no-OS:`Example adv7511_zc706 no-Os software <projects/adv7511>`).
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Examples for different data width configurations
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-------------------------------------------------------------------------------
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The :adi:`ADV7511 <media/en/technical-documentation/user-guides/ADV7511_Hardware_Users_Guide.pdf>`
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can accept video data from as few as eight pins (either YCbCr 4:2:2 double data
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rate [DDR] or YCbCr 4:2:2 with 2x pixel clock) to as many as 36 pins (RGB 4:4:4
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or YCbCr 4:4:4). In addition it can accept HSYNC, VSYNC and DE (Data Enable)
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The **axi_hdmi_tx** core support the following video input connections:
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* 36 bits with HSYNC, VSYNC and DE (:git-hdl:`hdl_2017_r1:projects/adv7511/vc707` development board)
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* 24 bits with HSYNC, VSYNC and DE (:git-hdl:`projects/adv7511/zc706` development board)
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* 16 bits with HSYNC, VSYNC and DE (:git-hdl:`projects/adv7511/zed`)
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* 16 bits with embedded SYNC (TX interface of the :git-hdl:`IMAGEON <projects/imageon>` board)
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Software support
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-------------------------------------------------------------------------------
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The core can be controlled by no-Os or Linux
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* :dokuwiki:`Linux Driver <resources/tools-software/linux-drivers/drm/adv7511>`
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* :dokuwiki:`Reference design with no-OS example <resources/fpga/xilinx/kc705/adv7511>`
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* :git-no-OS:`projects/adv7511`
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References
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-------------------------------------------------------------------------------
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* :git-hdl:`library/axi_hdmi_tx`
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* :dokuwiki:`Zynq & Altera SoC Quick Start Guide <resources/tools-software/linux-software/kuiper-linux>`
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* :dokuwiki:`FMC-IMAGEON Xilinx Reference Design <resources/fpga/xilinx/fmc/fmc-imageon>`
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* :dokuwiki:`ADV7511 Xilinx Evaluation Boards Reference Design <resources/fpga/xilinx/kc705/adv7511>`
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