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pluto_hdl_adi/docs/regmap/adi_regmap_adc.txt

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TITLE
ADC Common (axi_ad*)
ADC_COMMON
ENDTITLE
############################################################################################
############################################################################################
REG
0x0010
RSTN
ADC Interface Control & Status
ENDREG
FIELD
[2] 0x00000000
CE_N
RW
Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of
the module to control clock enables
ENDFIELD
FIELD
[1] 0x00000000
MMCM_RSTN
RW
MMCM reset only (required for DRP access).
Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
ENDFIELD
FIELD
[0] 0x00000000
RSTN
RW
Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0011
CNTRL
ADC Interface Control & Status
ENDREG
FIELD
[16] 0x00000000
SDR_DDR_N
RW
Interface type (1 represents SDR, 0 represents DDR)
ENDFIELD
FIELD
[15] 0x00000000
SYMB_OP
RW
Select symbol data format mode (0x1)
ENDFIELD
FIELD
[14] 0x00000000
SYMB_8_16B
RW
Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b)
ENDFIELD
FIELD
[12:8] 0x00000000
NUM_LANES
RW
Number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane).
For AD7768, AD7768-4 and AD777x number of active lanes : 1/2/4/8 where supported.
ENDFIELD
FIELD
[3] 0x00000000
SYNC
RW
Initialize synchronization between multiple ADCs
ENDFIELD
FIELD
[2] 0x00000000
R1_MODE
RW
Select number of RF channels 1 (0x1) or 2 (0x0).
ENDFIELD
FIELD
[1] 0x00000000
DDR_EDGESEL
RW
Select rising edge (0x0) or falling edge (0x1) for the first part
of a sample (if applicable) followed by the successive edges for
the remaining parts. This only controls how the sample is delineated
from the incoming data post DDR registers.
ENDFIELD
FIELD
[0] 0x00000000
PIN_MODE
RW
Select interface pin mode to be clock multiplexed (0x1) or pin
multiplexed (0x0). In clock multiplexed mode, samples are received
on alternative clock edges. In pin multiplexed mode, samples are
interleaved or grouped on the pins at the same clock edge.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0012
CNTRL_2
ADC Interface Control & Status
ENDREG
FIELD
[1] 0x00000000
EXT_SYNC_ARM
RW
Setting this bit will arm the trigger mechanism sensitive to an external sync signal.
Once the external sync signal goes high it synchronizes channels within a ADC, and across multiple instances.
This bit has an effect only the EXT_SYNC synthesis parameter is set.
This bit self clears.
ENDFIELD
FIELD
[2] 0x00000000
EXT_SYNC_DISARM
RW
Setting this bit will disarm the trigger mechanism sensitive to an external sync signal.
This bit has an effect only the EXT_SYNC synthesis parameter is set.
This bit self clears.
ENDFIELD
FIELD
[8] 0x00000000
MANUAL_SYNC_REQUEST
RW
Setting this bit will issue an external sync event if it is hooked up inside the fabric.
This bit has an effect only the EXT_SYNC synthesis parameter is set.
This bit self clears.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0013
CNTRL_3
ADC Interface Control & Status
ENDREG
FIELD
[8] 0x00000000
CRC_EN
RW
Setting this bit will enable the CRC generation.
ENDFIELD
FIELD
[7:0] 0x00000000
CUSTOM_CONTROL
RW
Select output format decode mode.(for ADAQ8092: bit 0 - enables digital output randomizer decode
, bit 1 - enables alternate bit polarity decode).
ENDFIELD
############################################################################################
############################################################################################
REG
0x0015
CLK_FREQ
ADC Interface Control & Status
ENDREG
FIELD
[31:0] 0x00000000
CLK_FREQ
RO
Interface clock frequency. This is relative to the processor clock and in many cases is
100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor
clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock
is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be
the same as the interface clock- software must consider device specific implementation
parameters to calculate the final sampling clock.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0016
CLK_RATIO
ADC Interface Control & Status
ENDREG
FIELD
[31:0] 0x00000000
CLK_RATIO
RO
Interface clock ratio - as a factor actual received clock. This is implementation specific
and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
ENDFIELD
############################################################################################
############################################################################################
REG
0x0017
STATUS
ADC Interface Control & Status
ENDREG
FIELD
[4] 0x00000000
ADC_CTRL_STATUS
RO
If set, indicates that the device'​s register data is available on the data bus.
ENDFIELD
FIELD
[3] 0x00000000
PN_ERR
RO
If set, indicates pn error in one or more channels.
ENDFIELD
FIELD
[2] 0x00000000
PN_OOS
RO
If set, indicates pn oos in one or more channels.
ENDFIELD
FIELD
[1] 0x00000000
OVER_RANGE
RO
If set, indicates over range in one or more channels.
ENDFIELD
FIELD
[0] 0x00000000
STATUS
RO
Interface status, if set indicates no errors. If not set, there
are errors, software may try resetting the cores.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0018
DELAY_CNTRL
ADC Interface Control & Status(''Deprecated from version 9'')
ENDREG
FIELD
[17] 0x00000000
DELAY_SEL
RW
Delay select, a 0x0 to 0x1 transition in this register initiates
a delay access controlled by the registers below.
ENDFIELD
FIELD
[16] 0x00000000
DELAY_RWN
RW
Delay read (0x1) or write (0x0), the delay is accessed directly
(no increment or decrement) with an address corresponding to each pin,
and data corresponding to the total delay.
ENDFIELD
FIELD
[15:8] 0x00000000
DELAY_ADDRESS
RW
Delay address, the range depends on the interface pins, data pins
are usually at the lower range.
ENDFIELD
FIELD
[4:0] 0x00000000
DELAY_WDATA
RW
Delay write data, a value of 1 corresponds to (1/200)ns for most devices.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0019
DELAY_STATUS
ADC Interface Control & Status(''Deprecated from version 9'')
ENDREG
FIELD
[9] 0x00000000
DELAY_LOCKED
RO
Indicates delay locked (0x1) state. If this bit is read 0x0, delay control
has failed to calibrate the elements.
ENDFIELD
FIELD
[8] 0x00000000
DELAY_STATUS
RO
If set, indicates busy status (access pending). The read data may not be
valid if this bit is set.
ENDFIELD
FIELD
[4:0] 0x00000000
DELAY_RDATA
RO
Delay read data, current delay value in the elements
ENDFIELD
############################################################################################
############################################################################################
REG
0x001A
SYNC_STATUS
ADC Synchronization Status register
ENDREG
FIELD
[0] 0x00000000
ADC_SYNC
RO
ADC synchronization status. Will be set to 1 after the synchronization has been completed
or while waiting for the synchronization signal in JESD204 systems.
ENDFIELD
############################################################################################
############################################################################################
REG
0x001C
DRP_CNTRL
ADC Interface Control & Status
ENDREG
FIELD
[28] 0x00000000
DRP_RWN
RW
DRP read (0x1) or write (0x0) select (does not include GTX lanes).
NOT-APPLICABLE if DRP_DISABLE is set (0x1).
ENDFIELD
FIELD
[27:16] 0x00000000
DRP_ADDRESS
RW
DRP address, designs that contain more than one DRP accessible primitives
have selects based on the most significant bits (does not include GTX lanes).
NOT-APPLICABLE if DRP_DISABLE is set (0x1).
ENDFIELD
FIELD
[15:0] 0x00000000
RESERVED
RO
Reserved for backward compatibility.
ENDFIELD
############################################################################################
############################################################################################
REG
0x001D
DRP_STATUS
ADC Interface Control & Status
ENDREG
FIELD
[17] 0x00000000
DRP_LOCKED
RO
If set indicates that the DRP has been locked.
ENDFIELD
FIELD
[16] 0x00000000
DRP_STATUS
RO
If set indicates busy (access pending). The read data may not be valid if
this bit is set (does not include GTX lanes).
NOT-APPLICABLE if DRP_DISABLE is set (0x1).
ENDFIELD
FIELD
[15:0] 0x00000000
RESERVED
RO
Reserved for backward compatibility.
ENDFIELD
############################################################################################
############################################################################################
REG
0x001E
DRP_WDATA
ADC DRP Write Data
ENDREG
FIELD
[15:0] 0x00000000
DRP_WDATA
RW
DRP write data (does not include GTX lanes).
NOT-APPLICABLE if DRP_DISABLE is set (0x1).
ENDFIELD
############################################################################################
############################################################################################
REG
0x001F
DRP_RDATA
ADC DRP Read Data
ENDREG
FIELD
[15:0] 0x00000000
DRP_RDATA
RO
DRP read data (does not include GTX lanes).
ENDFIELD
############################################################################################
############################################################################################
REG
0x0020
ADC_CONFIG_WR
ADC Write Configuration ​Data
ENDREG
FIELD
[31:0] 0x00000000
ADC_CONFIG_WR
RW
Custom ​Write to the available registers.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0021
ADC_CONFIG_RD
ADC Read Configuration ​Data
ENDREG
FIELD
[31:0] 0x00000000
ADC_CONFIG_RD
RO
Custom read of the available registers.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0022
UI_STATUS
User Interface Status
ENDREG
FIELD
[2] 0x00000000
UI_OVF
RW1C
User Interface overflow. If set, indicates an overflow occurred during data transfer at
the user interface (FIFO interface). Software must write a 0x1 to clear this register
bit.
ENDFIELD
FIELD
[1] 0x00000000
UI_UNF
RW1C
User Interface underflow. If set, indicates an underflow occurred during data transfer at
the user interface (FIFO interface). Software must write a 0x1 to clear this register
bit.
ENDFIELD
FIELD
[0] 0x00000000
UI_RESERVED
RW1C
Reserved for backward compatibility.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0023
ADC_CONFIG_CTRL
ADC RD/WR configuration
ENDREG
FIELD
[31:0] 0x00000000
ADC_CONFIG_CTRL
RW
Control RD/WR requests to the device'​s register map: bit 1 - RD ('b1) , WR ('b0), bit 0 - enable WR/RD operation.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0028
USR_CNTRL_1
ADC Interface Control & Status
ENDREG
FIELD
[7:0] 0x00000000
USR_CHANMAX
RW
This indicates the maximum number of inputs for the channel data multiplexers. User may add
different processing modules post data capture as another input to this common multiplexer.
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
ENDFIELD
############################################################################################
############################################################################################
REG
0x0029
ADC_START_CODE
ADC Synchronization start word
ENDREG
FIELD
[31:0] 0x00000000
ADC_START_CODE
RW
This sets the startcode that is used by the ADCs for synchronization
NOT-APPLICABLE if START_CODE_DISABLE is set (0x1).
ENDFIELD
############################################################################################
############################################################################################
REG
0x002E
ADC_GPIO_IN
ADC GPIO inputs
ENDREG
FIELD
[31:0] 0x00000000
ADC_GPIO_IN
RO
This reads auxiliary GPI pins of the ADC core
ENDFIELD
############################################################################################
############################################################################################
REG
0x002F
ADC_GPIO_OUT
ADC GPIO outputs
ENDREG
FIELD
[31:0] 0x00000000
ADC_GPIO_OUT
RW
This controls auxiliary GPO pins of the ADC core
NOT-APPLICABLE if GPIO_DISABLE is set (0x1).
ENDFIELD
############################################################################################
############################################################################################
REG
0x0030
PPS_COUNTER
PPS Counter register
ENDREG
FIELD
[31:0] 0x00000000
PPS_COUNTER
RO
Counts the core clock cycles (can be a device clock or interface clock) between two 1PPS pulse.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0031
PPS_STATUS
PPS Status register
ENDREG
FIELD
[0] 0x00000000
PPS_STATUS
RO
If this bit is asserted there is no incomming 1PPS signal. Maybe the source is out of sync or it's not active.
ENDFIELD
############################################################################################
############################################################################################
TITLE
ADC Channel (axi_ad*)
ADC_CHANNEL
ENDTITLE
############################################################################################
############################################################################################
REG
0x0100 + 0x16*n
WHERE n IS FROM 0 TO 15
CHAN_CNTRLn
ADC Interface Control & Status
ENDREG
FIELD
[11] 0x00000000
ADC_LB_OWR
RW
If set, forces ADC_DATA_SEL to 1, enabling data loopback
ENDFIELD
FIELD
[10] 0x00000000
ADC_PN_SEL_OWR
RW
If set, forces ADC_PN_SEL to 0x9, device specific pn (e.g. ad9361)
If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored
ENDFIELD
FIELD
[9] 0x00000000
IQCOR_ENB
RW
if set, enables IQ correction or scale correction.
NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
ENDFIELD
FIELD
[8] 0x00000000
DCFILT_ENB
RW
if set, enables DC filter (to disable DC offset, set offset value to 0x0).
NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).
ENDFIELD
FIELD
[6] 0x00000000
FORMAT_SIGNEXT
RW
if set, enables sign extension (applicable only in 2's complement mode). The data is
always sign extended to the nearest byte boundary.
NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).
ENDFIELD
FIELD
[5] 0x00000000
FORMAT_TYPE
RW
Select offset binary (0x1) or 2's complement (0x0) data type. This sets the incoming
data type and is required by the post processing modules for any data conversion.
NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).
ENDFIELD
FIELD
[4] 0x00000000
FORMAT_ENABLE
RW
Enable data format conversion (see register bits above).
NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).
ENDFIELD
FIELD
[3] 0x00000000
RESERVED
RO
Reserved for backward compatibility.
ENDFIELD
FIELD
[2] 0x00000000
RESERVED
RO
Reserved for backward compatibility.
ENDFIELD
FIELD
[1] 0x00000000
ADC_PN_TYPE_OWR
RW
If set, forces ADC_PN_SEL to 0x1, modified pn23
If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored
ENDFIELD
FIELD
[0] 0x00000000
ENABLE
RW
If set, enables channel. A 0x0 to 0x1 transition transfers all the control signals
to the respective channel processing module. If a channel is part of a complex
signal (I/Q), even channel is the master and the odd channel is the slave.
Though a single control is used, both must be individually selected.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0101 + 0x16*n
WHERE n IS FROM 0 TO 15
CHAN_STATUSn
ADC Interface Control & Status
ENDREG
FIELD
[12] 0x00000000
CRC_ERR
RW1C
CRC errors. If set, indicates CRC error. Software must first clear this bit before initiating a transfer and monitor afterwards.
ENDFIELD
FIELD
[11:4] 0x00000000
STATUS_HEADER
RO
The status header sent by the ADC.(compatible with AD7768/AD7768-4/AD777x).
ENDFIELD
FIELD
[2] 0x00000000
PN_ERR
RW1C
PN errors. If set, indicates spurious mismatches in sync state. This bit is cleared
if OOS is set and is only indicates errors when OOS is cleared.
ENDFIELD
FIELD
[1] 0x00000000
PN_OOS
RW1C
PN Out Of Sync. If set, indicates an OOS status. OOS is set, if 64 consecutive patterns
mismatch from the expected pattern. It is cleared, when 16 consecutive patterns match
the expected pattern.
ENDFIELD
FIELD
[0] 0x00000000
OVER_RANGE
RW1C
If set, indicates over range. Note that over range is independent of the data path,
it indicates an over range over a data transfer period. Software must first clear
this bit before initiating a transfer and monitor afterwards.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0102 + 0x16*n
WHERE n IS FROM 0 TO 15
CHAN_RAW_DATAn
ADC Raw Data Reading
ENDREG
FIELD
[31:0] 0x00000000
ADC_READ_DATA
RO
Raw data read from the ADC.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0104 + 0x16*n
WHERE n IS FROM 0 TO 15
CHAN_CNTRLn_1
ADC Interface Control & Status
ENDREG
FIELD
[31:16] 0x00000000
DCFILT_OFFSET
RW
DC removal (if equipped) offset. This is a 2's complement number added to the incoming
data to remove a known DC offset.
NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).
ENDFIELD
FIELD
[15:0] 0x00000000
DCFILT_COEFF
RW
DC removal filter (if equipped) coefficient. The format is 1.1.14 (sign, integer and
fractional bits).
NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).
ENDFIELD
############################################################################################
############################################################################################
REG
0x0105 + 0x16*n
WHERE n IS FROM 0 TO 15
CHAN_CNTRLn_2
ADC Interface Control & Status
ENDREG
FIELD
[31:16] 0x00000000
IQCOR_COEFF_1
RW
IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value
and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used,
this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits).
If SCALECORRECTION_ONLY is set, this implements the scale value correction for the current channel
with the format 1.1.14 (sign, integer and fractional bits).
NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
ENDFIELD
FIELD
[15:0] 0x00000000
IQCOR_COEFF_2
RW
IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value
and the format is 2's complement. If matrix multiplication is used, this is the channel Q coefficient
and the format is 1.1.14 (sign, integer and fractional bits).
NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
ENDFIELD
############################################################################################
############################################################################################
REG
0x0106 + 0x16*n
WHERE n IS FROM 0 TO 15
CHAN_CNTRLn_3
ADC Interface Control & Status
ENDREG
FIELD
[19:16] 0x00000000
ADC_PN_SEL
RW
Selects the PN monitor sequence type (available only if ADC supports it). \\
- 0x0: pn9a (device specific, modified pn9) \\
- 0x1: pn23a (device specific, modified pn23) \\
- 0x4: pn7 (standard O.150) \\
- 0x5: pn15 (standard O.150) \\
- 0x6: pn23 (standard O.150) \\
- 0x7: pn31 (standard O.150) \\
- 0x9: pnX (device specific, e.g. ad9361) \\
- 0x0A: Nibble ramp (Device specific e.g. adrv9001) \\
- 0x0B: 16 bit ramp (Device specific e.g. adrv9001) \\
ENDFIELD
FIELD
[3:0] 0x00000000
ADC_DATA_SEL
RW
Selects the data source to DMA.
0x0: input data (ADC)
0x1: loopback data (DAC)
ENDFIELD
############################################################################################
############################################################################################
REG
0x0108 + 0x16*n
WHERE n IS FROM 0 TO 15
CHAN_USR_CNTRLn_1
ADC Interface Control & Status
ENDREG
FIELD
[25] 0x00000000
USR_DATATYPE_BE
RO
The user data type format- if set, indicates big endian (default is little endian).
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
ENDFIELD
FIELD
[24] 0x00000000
USR_DATATYPE_SIGNED
RO
The user data type format- if set, indicates signed (2's complement) data (default is unsigned).
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
ENDFIELD
FIELD
[23:16] 0x00000000
USR_DATATYPE_SHIFT
RO
The user data type format- the amount of right shift for actual samples within the total number
of bits.
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
ENDFIELD
FIELD
[15:8] 0x00000000
USR_DATATYPE_TOTAL_BITS
RO
The user data type format- number of total bits used for a sample. The total number of bits must
be an integer multiple of 8 (byte aligned).
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
ENDFIELD
FIELD
[7:0] 0x00000000
USR_DATATYPE_BITS
RO
The user data type format- number of bits in a sample. This indicates the actual sample data bits.
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
ENDFIELD
############################################################################################
############################################################################################
REG
0x0109 + 0x16*n
WHERE n IS FROM 0 TO 15
CHAN_USR_CNTRLn_2
ADC Interface Control & Status
ENDREG
FIELD
[31:16] 0x00000000
USR_DECIMATION_M
RW
This holds the user decimation M value of the channel that is currently being selected on
the multiplexer above. The total decimation factor is of the form M/N.
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
ENDFIELD
FIELD
[15:0] 0x00000000
USR_DECIMATION_N
RW
This holds the user decimation N value of the channel that is currently being selected on
the multiplexer above. The total decimation factor is of the form M/N.
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
ENDFIELD
############################################################################################
############################################################################################
REG
0x010A + 0x16*n
WHERE n IS FROM 0 TO 15
CHAN_CNTRLn_4
ADC Interface Control & Status
ENDREG
FIELD
[31:3] 0x00000000
RESERVED
RO
Reserved for backward compatibility.
ENDFIELD
FIELD
[2:0] 0x00000007
SOFTSPAN
RW
Softspan configuration register.
ENDFIELD
############################################################################################
############################################################################################
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