828 lines
15 KiB
Plaintext
828 lines
15 KiB
Plaintext
TITLE
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JESD204 TX (axi_jesd204_tx)
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JESD_TX
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ENDTITLE
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############################################################################################
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############################################################################################
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REG
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0x00
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VERSION
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Version of the peripheral. Follows semantic versioning. Current version 1.03.a.
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ENDREG
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FIELD
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[31:16] 0x00000001
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VERSION_MAJOR
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RO
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ENDFIELD
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FIELD
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[15:8] 0x00000003
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VERSION_MINOR
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RO
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ENDFIELD
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FIELD
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[7:0] 0x00000061
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VERSION_PATCH
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RO
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x01
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PERIPHERAL_ID
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ENDREG
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FIELD
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[31:0]
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PERIPHERAL_ID
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RO
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Value of the ID configuration parameter.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x02
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SCRATCH
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ENDREG
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FIELD
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[31:0] 0x00000000
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SCRATCH
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RW
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Scratch register useful for debug.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x03
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IDENTIFICATION
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ENDREG
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FIELD
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[31:0] 0x32303454
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IDENTIFICATION
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RO
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Peripheral identification ('2', '0', '4', 'T').
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x04
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SYNTH_NUM_LANES
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ENDREG
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FIELD
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[31:0]
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SYNTH_NUM_LANES
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RO
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Number of supported lanes.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x05
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SYNTH_DATA_PATH_WIDTH
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ENDREG
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FIELD
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[31:16] 0x00000000
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RESERVED
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RO
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ENDFIELD
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FIELD
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[15:8] 0x00000002
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TPL_DATA_PATH_WIDTH
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RO
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Data path width in octets at Transport Layer interface. Available starting from version 1.06.a;
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ENDFIELD
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FIELD
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[7:0] 0x00000002
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SYNTH_DATA_PATH_WIDTH
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RO
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Log2 of internal data path width in octets. Represents the datapath width towards the physical interface.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x06
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SYNTH_1
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Core description register.
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ENDREG
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FIELD
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[31:19] 0x00000000
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RESERVED
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RO
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ENDFIELD
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FIELD
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[18] 0x00000000
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ENABLE_CHAR_REPLACE
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RO
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This bit reflects the presence of character replacement insertion logic for cases when scrambling is disabled.
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Available starting from version 1.06.a;
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ENDFIELD
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FIELD
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[12] ''ASYNC_CLK''
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ASYNC_CLK
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RO
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This bit is set if link clock and device clock are connected to different sources.
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This is useful for supporting modes where datapath width is not integer multiple of F.
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Available starting from version 1.06.a;
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ENDFIELD
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FIELD
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[9:8]
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ENCODER
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RO
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Encoder presence: 01 - 8B10B encoder \\ 10 - 64B66B encoder
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ENDFIELD
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FIELD
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[7:0]
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NUM_LINKS
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RO
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Maximum supported links. Valid for 8B/10B link.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x20
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IRQ_ENABLE
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ENDREG
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FIELD
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[31:0] 0x00000000
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IRQ_ENABLE
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RW
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Interrupt enable.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x21
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IRQ_PENDING
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ENDREG
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FIELD
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[31:0] 0x00000000
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IRQ_PENDING
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RW1C-V
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Pending and enabled interrupts.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x22
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IRQ_SOURCE
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ENDREG
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FIELD
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[31:0] 0x00000000
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IRQ_SOURCE
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RW1C-V
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Pending interrupts.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x30
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LINK_DISABLE
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JESD204B link disable.
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ENDREG
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FIELD
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[31:1] 0x00000000
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RESERVED
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RO
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ENDFIELD
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FIELD
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[0] 0x00000001
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LINK_DISABLE
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RW
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0 = Enable link, 1 = Disable link.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x31
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LINK_STATE
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JESD204B link state.
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ENDREG
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FIELD
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[31:2] 0x00000000
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RESERVED
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RO
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ENDFIELD
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FIELD
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[1]
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EXTERNAL_RESET
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RO
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0 = External reset de-asserted, 1 = External reset asserted.
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ENDFIELD
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FIELD
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[0] 0x00000001
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LINK_STATE
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RO
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0 = Link enabled, 1 = Link disabled.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x32
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LINK_CLK_FREQ
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ENDREG
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FIELD
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[31:0]
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LINK_CLK_FREQ
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RO-V
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Ratio of the link_clk frequency relative to the s_axi_aclk. Format is 16.16.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x33
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DEVICE_CLK_FREQ
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ENDREG
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FIELD
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[20:0]
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DEVICE_CLK_FREQ
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RO-V
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Ratio of the device_clk frequency relative to the s_axi_aclk. Format is 16.16.
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Available starting from version 1.06.a;
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x40
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SYSREF_CONF
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SYSREF configuration
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ENDREG
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FIELD
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[31:2] 0x00000000
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RESERVED
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RO
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ENDFIELD
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FIELD
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[1] 0x00000000
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SYSREF_ONESHOT
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RW
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In oneshot mode only the first occurrence of the SYSREF signal is used for alignment.
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ENDFIELD
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FIELD
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[0] 0x00000000
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SYSREF_DISABLE
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RW
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Enable/Disable SYSREF handling.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x41
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SYSREF_LMFC_OFFSET
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SYSREF LMFC offset
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ENDREG
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FIELD
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[31:10] 0x00000000
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RESERVED
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RO
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ENDFIELD
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FIELD
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[9:0] 0x00000000
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SYSREF_LMFC_OFFSET
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RW
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Offset between SYSREF event and internal LMFC event in octets.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x42
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SYSREF_STATUS
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SYSREF status
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ENDREG
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FIELD
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[31:2] 0x00000000
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RESERVED
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RO
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ENDFIELD
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FIELD
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[1] 0x00000000
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SYSREF_ALIGNMENT_ERROR
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RW1C-V
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Indicates that an external SYSREF event has been observed that was unaligned to a previously
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observed event.
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ENDFIELD
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FIELD
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[0] 0x00000000
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SYSREF_DETECTED
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RW1C-V
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Indicates that an external SYSREF event has been observed.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x80
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LANES_DISABLE
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Enabled/Disabled lanes.
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ENDREG
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FIELD
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[n] 0x00000000
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WHERE n IS FROM 0 TO 31
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LANE_DISABLEn
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RW
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Enable/Disable n-th lane (0 = enabled, 1 = disabled).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x84
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LINK_CONF0
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JESD204B link configuration.
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ENDREG
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FIELD
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[31:19] 0x00000000
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RESERVED
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RO
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ENDFIELD
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FIELD
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[18:16] 0x00000000
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OCTETS_PER_FRAME
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RW
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Number of octets per frame - 1 (F).
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ENDFIELD
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FIELD
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[15:10] 0x00000000
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RESERVED
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RO
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ENDFIELD
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FIELD
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[9:0] 0x00000003
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OCTETS_PER_MULTIFRAME
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RW
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Number of octets per multi-frame - 1 (K x F).
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In 64B/66B mode represents the number of octets per extended multiblock.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x85
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LINK_CONF1
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JESD204B link configuration.
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ENDREG
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FIELD
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[31:2] 0x00000000
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RESERVED
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RO
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ENDFIELD
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FIELD
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[1] 0x00000000
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CHAR_REPLACEMENT_DISABLE
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RW
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Enable/Disable user data alignment character replacement (0 = enabled, 1 = disabled).
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Valid for 8B/10B link.
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ENDFIELD
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FIELD
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[0] 0x00000000
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SCRAMBLER_DISABLE
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RW
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Enable/Disable user data descrambling (0 = enabled, 1 = disabled).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x86
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MULTI_LINK_DISABLE
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Enable/Disable links in case of a multi-link architecture.
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Valid for 8B/10B link.
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ENDREG
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FIELD
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[n] 0x00000000
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WHERE n IS FROM 0 TO 31
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LINK_DISABLEn
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RW
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Enable/Disable n-th link (0 = enabled, 1 = disabled).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x87
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LINK_CONF4
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JESD204B link configuration.
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ENDREG
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FIELD
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[31:8] 0x00000000
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RESERVED
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RO
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ENDFIELD
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FIELD
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[7:0] 0x00000000
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TPL_BEATS_PER_MULTIFRAME
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RW
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Number of beats per multi-frame - 1 (K x F / TPL_DATA_PATH_WIDTH) at interface to Transport Layer.
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In 64B/66B mode represents the number of octets per extended multiblock.
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Available starting from version 1.06.a;
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x90
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LINK_CONF2
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JESD204B link configuration. Valid for 8B/10B link.
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ENDREG
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FIELD
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[31:3] 0x00000000
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RESERVED
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RO
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ENDFIELD
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FIELD
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[2] 0x00000000
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SKIP_ILAS
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RW
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Skip ILAS sequence during link startup.
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ENDFIELD
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FIELD
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[1] 0x00000000
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CONTINUOUS_ILAS
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RW
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Continuously transmit ILAS sequence.
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ENDFIELD
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FIELD
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[0] 0x00000000
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CONTINUOUS_CGS
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RW
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Continuously transmit CGS sequence.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x91
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LINK_CONF3
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JESD204B link configuration. Valid for 8B/10B link.
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ENDREG
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FIELD
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[31:8] 0x00000000
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RESERVED
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RO
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ENDFIELD
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FIELD
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[7:0] 0x00000003
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MFRAMES_PER_ILAS
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RW
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Number of multi-frames in the ILAS sequence - 1.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x92
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MANUAL_SYNC_REQUEST
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Manual synchronization request. Valid for 8B/10B link.
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ENDREG
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FIELD
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[31:1] 0x00000000
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RESERVED
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RO
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ENDFIELD
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FIELD
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[0] 0x00000000
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MANUAL_SYNC_REQUEST
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W1S
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Trigger manual synchronization request.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0xa0
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LINK_STATUS
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JESD204B link status.
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ENDREG
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FIELD
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[31:12] 0x00000000
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RESERVED
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RO
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ENDFIELD
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FIELD
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[11:4]
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STATUS_SYNC
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RO-V
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Raw state of the external SYNC~ signals. Valid for 8B/10B link.
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ENDFIELD
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FIELD
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[3:2] 0x00000000
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RESERVED
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RO
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ENDFIELD
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FIELD
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[1:0] 0x00000000
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STATUS_STATE
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RO-V
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State of the 8B/10B link state machine. (0 = WAIT, 1 = CGS, 2 = ILAS, 3 = DATA);
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State of the 64B/66B link state machine. (0 = RESET, 3 = DATA)
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0xc4 + 0x08*n
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WHERE n IS FROM 0 TO 31
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LANEn_ILAS0
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ILAS config data for the n-th lane. Valid for 8B/10B link.
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ENDREG
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FIELD
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[31:28] 0x00000000
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RESERVED
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RO
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ENDFIELD
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FIELD
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[27:24] 0x00000000
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BID
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RW
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BID (Bank ID) field of the ILAS config sequence.
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ENDFIELD
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FIELD
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[23:16] 0x00000000
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DID
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RW
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DID (Device ID) field of the ILAS config sequence.
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ENDFIELD
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FIELD
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[15:0] 0x00000000
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RESERVED
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RO
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0xc5 + 0x08*n
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WHERE n IS FROM 0 TO 31
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LANEn_ILAS1
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ILAS config data for the n-th lane. Valid for 8B/10B link.
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ENDREG
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FIELD
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[31:29] 0x00000000
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RESERVED
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RO
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ENDFIELD
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FIELD
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[28:24] 0x00000000
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K
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RW
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K (Frames per multi-frame) field of the ILAS config sequence - 1.
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ENDFIELD
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FIELD
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[23:16] 0x00000000
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F
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RW
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F (Octets per frame) field of the ILAS config sequence - 1.
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ENDFIELD
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|
|
FIELD
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[15] 0x00000000
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SCR
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RW
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SCR (Scrambling enabled) field of the ILAS config sequence.
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ENDFIELD
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|
|
FIELD
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[14:13] 0x00000000
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RESERVED
|
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RO
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ENDFIELD
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FIELD
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[12:8] 0x00000000
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L
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RW
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L (Number of lanes) field of the ILAS config sequence - 1.
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ENDFIELD
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|
FIELD
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[7:5] 0x00000000
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RESERVED
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RO
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ENDFIELD
|
|
|
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FIELD
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[4:0] 0x00000000
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LID
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RW
|
|
LID (Lane ID) field of the ILAS config sequence.
|
|
ENDFIELD
|
|
|
|
############################################################################################
|
|
############################################################################################
|
|
|
|
REG
|
|
0xc6 + 0x08*n
|
|
WHERE n IS FROM 0 TO 31
|
|
LANEn_ILAS2
|
|
ILAS config data for the n-th lane. Valid for 8B/10B link.
|
|
ENDREG
|
|
|
|
FIELD
|
|
[31:29] 0x00000000
|
|
JESDV
|
|
RW
|
|
JESDV (JESD204 version) field of the ILAS config sequence.
|
|
ENDFIELD
|
|
|
|
FIELD
|
|
[28:24] 0x00000000
|
|
S
|
|
RW
|
|
S (Samples per frame) field of the ILAS config sequence - 1.
|
|
ENDFIELD
|
|
|
|
FIELD
|
|
[23:21] 0x00000000
|
|
SUBCLASSV
|
|
RW
|
|
SUBCLASSV (JESD204B subclass) field of the ILAS config sequence.
|
|
ENDFIELD
|
|
|
|
FIELD
|
|
[20:16] 0x00000000
|
|
NP
|
|
RW
|
|
N' (Total number of bits per sample) field of the ILAS config sequence - 1.
|
|
ENDFIELD
|
|
|
|
FIELD
|
|
[15:14] 0x00000000
|
|
CS
|
|
RW
|
|
CS (Control bits per sample) field of the ILAS config sequence.
|
|
ENDFIELD
|
|
|
|
FIELD
|
|
[13] 0x00000000
|
|
RESERVED
|
|
RO
|
|
ENDFIELD
|
|
|
|
FIELD
|
|
[12:8] 0x00000000
|
|
N
|
|
RW
|
|
N (Converter resolution) field of the ILAS config sequence - 1.
|
|
ENDFIELD
|
|
|
|
FIELD
|
|
[7:0] 0x00000000
|
|
M
|
|
RW
|
|
M (Number of converters) field of the ILAS config sequence - 1.
|
|
ENDFIELD
|
|
|
|
############################################################################################
|
|
############################################################################################
|
|
|
|
REG
|
|
0xc7 + 0x08*n
|
|
WHERE n IS FROM 0 TO 31
|
|
LANEn_ILAS3
|
|
ILAS config data for the n-th lane. Valid for 8B/10B link.
|
|
ENDREG
|
|
|
|
FIELD
|
|
[31:24] 0x00000000
|
|
FCHK
|
|
RW
|
|
FCHK (Checksum) field of the ILAS config sequence.
|
|
ENDFIELD
|
|
|
|
FIELD
|
|
[23:8] 0x00000000
|
|
RESERVED
|
|
RO
|
|
ENDFIELD
|
|
|
|
FIELD
|
|
[7] 0x00000000
|
|
HD
|
|
RW
|
|
HD (High-density) field of the ILAS config sequence.
|
|
ENDFIELD
|
|
|
|
FIELD
|
|
[6:5] 0x00000000
|
|
RESERVED
|
|
RO
|
|
ENDFIELD
|
|
|
|
FIELD
|
|
[4:0] 0x00000000
|
|
CF
|
|
RO
|
|
CF (control words per frame) field of the ILAS config sequence
|
|
ENDFIELD
|
|
|
|
############################################################################################
|
|
############################################################################################
|