208 lines
6.1 KiB
Verilog
208 lines
6.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9434_if #(
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parameter FPGA_TECHNOLOGY = 0,
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parameter IODELAY_ENABLE = 1,
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parameter IO_DELAY_GROUP = "dev_if_delay_group"
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) (
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// device interface
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input adc_clk_in_p,
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input adc_clk_in_n,
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input [11:0] adc_data_in_p,
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input [11:0] adc_data_in_n,
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input adc_or_in_p,
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input adc_or_in_n,
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// interface outputs
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output [47:0] adc_data,
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output adc_or,
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// internl reset and clocks
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output adc_clk,
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input adc_rst,
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output reg adc_status,
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// delay interface (for IDELAY macros)
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input up_clk,
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input [12:0] up_adc_dld,
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input [64:0] up_adc_dwdata,
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output [64:0] up_adc_drdata,
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input delay_clk,
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input delay_rst,
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output delay_locked,
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// mmcm reset
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input mmcm_rst,
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// drp interface for MMCM_OR_BUFR_N
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input up_rstn,
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input up_drp_sel,
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input up_drp_wr,
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input [11:0] up_drp_addr,
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input [31:0] up_drp_wdata,
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output [31:0] up_drp_rdata,
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output up_drp_ready,
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output up_drp_locked
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);
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localparam SDR = 0;
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// internal registers
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reg adc_status_m1 = 'd0;
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// internal signals
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wire [3:0] adc_or_s;
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wire adc_clk_in;
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wire adc_div_clk;
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genvar l_inst;
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// output assignment for adc clock (1:4 of the sampling clock)
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assign adc_clk = adc_div_clk;
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// data interface
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ad_serdes_in #(
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.FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
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.IODELAY_ENABLE (IODELAY_ENABLE),
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.IODELAY_CTRL(0),
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.IODELAY_GROUP(IO_DELAY_GROUP),
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.DDR_OR_SDR_N(SDR),
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.DATA_WIDTH(12),
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.SERDES_FACTOR(4)
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) i_adc_data (
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.rst(adc_rst),
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.clk(adc_clk_in),
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.div_clk(adc_div_clk),
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.data_s0(adc_data[47:36]),
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.data_s1(adc_data[35:24]),
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.data_s2(adc_data[23:12]),
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.data_s3(adc_data[11: 0]),
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.data_s4(),
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.data_s5(),
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.data_s6(),
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.data_s7(),
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.data_in_p(adc_data_in_p),
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.data_in_n(adc_data_in_n),
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.up_clk (up_clk),
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.up_dld (up_adc_dld[11:0]),
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.up_dwdata (up_adc_dwdata[59:0]),
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.up_drdata (up_adc_drdata[59:0]),
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.delay_clk(delay_clk),
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.delay_rst(delay_rst),
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.delay_locked());
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// over-range interface
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ad_serdes_in #(
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.FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
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.IODELAY_ENABLE (IODELAY_ENABLE),
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.IODELAY_CTRL(1),
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.IODELAY_GROUP(IO_DELAY_GROUP),
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.DDR_OR_SDR_N(SDR),
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.DATA_WIDTH(1),
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.SERDES_FACTOR(4)
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) i_adc_or (
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.rst(adc_rst),
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.clk(adc_clk_in),
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.div_clk(adc_div_clk),
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.data_s0(adc_or_s[3]),
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.data_s1(adc_or_s[2]),
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.data_s2(adc_or_s[1]),
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.data_s3(adc_or_s[0]),
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.data_s4(),
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.data_s5(),
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.data_s6(),
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.data_s7(),
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.data_in_p(adc_or_in_p),
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.data_in_n(adc_or_in_n),
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.up_clk (up_clk),
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.up_dld (up_adc_dld[12]),
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.up_dwdata (up_adc_dwdata[64:60]),
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.up_drdata (up_adc_drdata[64:60]),
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.delay_clk(delay_clk),
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.delay_rst(delay_rst),
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.delay_locked(delay_locked));
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// clock input buffers and MMCM_OR_BUFR_N
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ad_serdes_clk #(
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.CLKIN_DS_OR_SE_N (1),
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.MMCM_OR_BUFR_N (1),
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.MMCM_CLKIN_PERIOD (2),
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.MMCM_VCO_DIV (6),
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.MMCM_VCO_MUL (12),
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.MMCM_CLK0_DIV (2),
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.MMCM_CLK1_DIV (8),
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.SERDES_FACTOR(4)
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) i_serdes_clk (
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.rst (mmcm_rst),
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.clk_in_p (adc_clk_in_p),
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.clk_in_n (adc_clk_in_n),
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.clk (adc_clk_in),
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.div_clk (adc_div_clk),
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.out_clk (),
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.up_clk (up_clk),
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.up_rstn (up_rstn),
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.up_drp_sel (up_drp_sel),
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.up_drp_wr (up_drp_wr),
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.up_drp_addr (up_drp_addr),
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.up_drp_wdata (up_drp_wdata),
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.up_drp_rdata (up_drp_rdata),
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.up_drp_ready (up_drp_ready),
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.up_drp_locked (up_drp_locked));
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// adc over range
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assign adc_or = adc_or_s[0] | adc_or_s[1] | adc_or_s[2] | adc_or_s[3];
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// adc status: adc is up, if both the MMCM_OR_BUFR_N and DELAY blocks are up
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always @(posedge adc_div_clk) begin
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if (adc_rst == 1'b1) begin
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adc_status_m1 <= 1'b0;
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adc_status <= 1'b0;
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end else begin
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adc_status_m1 <= up_drp_locked & delay_locked;
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adc_status <= adc_status_m1;
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end
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end
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endmodule
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