151 lines
4.9 KiB
Systemverilog
151 lines
4.9 KiB
Systemverilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module axi_tdd_sync_gen #(
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parameter SYNC_INTERNAL = 1,
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parameter SYNC_EXTERNAL = 0,
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parameter SYNC_EXTERNAL_CDC = 0,
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parameter SYNC_COUNT_WIDTH = 64
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) (
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input logic clk,
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input logic resetn,
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input logic sync_in,
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output logic sync_out,
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input logic tdd_enable,
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input logic tdd_sync_ext,
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input logic tdd_sync_int,
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input logic tdd_sync_soft,
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input logic [SYNC_COUNT_WIDTH-1:0] asy_tdd_sync_period
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);
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// internal signals
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logic [1:0] sync_source;
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// Connect the enable signal to the enable flop lines
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(* direct_enable = "yes" *) logic enable;
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assign enable = tdd_enable;
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// first sync source (external)
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generate
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if (SYNC_EXTERNAL == 1) begin
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if (SYNC_EXTERNAL_CDC == 1) begin
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logic tdd_sync_m1 = 1'b0;
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logic tdd_sync_m2 = 1'b0;
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logic tdd_sync_m3 = 1'b0;
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// synchronization of sync_in
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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tdd_sync_m1 <= 1'b0;
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tdd_sync_m2 <= 1'b0;
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tdd_sync_m3 <= 1'b0;
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end else begin
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tdd_sync_m1 <= sync_in;
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tdd_sync_m2 <= tdd_sync_m1;
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tdd_sync_m3 <= tdd_sync_m2;
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end
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end
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assign sync_source[0] = ~tdd_sync_m3 & tdd_sync_m2;
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end else begin
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assign sync_source[0] = sync_in;
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end
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end else begin
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assign sync_source[0] = 1'b0;
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end
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endgenerate
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// second sync source (internal)
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generate
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if (SYNC_INTERNAL == 1) begin
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logic tdd_sync_trigger = 1'b0;
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logic [SYNC_COUNT_WIDTH-1:0] tdd_sync_counter = '0;
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logic [SYNC_COUNT_WIDTH-1:0] tdd_sync_period = '0;
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// Save the async register values only when the module is enabled
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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tdd_sync_period <= '0;
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end else begin
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if (enable) begin
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tdd_sync_period <= asy_tdd_sync_period;
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end
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end
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end
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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tdd_sync_trigger <= 1'b0;
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end else begin
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if (tdd_sync_counter == (tdd_sync_period - 1'b1)) begin
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tdd_sync_trigger <= 1'b1;
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end else begin
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tdd_sync_trigger <= 1'b0;
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end
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end
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end
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// sync counter
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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tdd_sync_counter <= '0;
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end else begin
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if (tdd_enable) begin
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tdd_sync_counter <= (tdd_sync_trigger == 1'b1) ? '0 : tdd_sync_counter + 1'b1;
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end else begin
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tdd_sync_counter <= '0;
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end
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end
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end
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assign sync_source[1] = tdd_sync_trigger;
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end else begin
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assign sync_source[1] = 1'b0;
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end
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endgenerate
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// creating the output sync signal
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assign sync_out = (tdd_sync_ext & sync_source[0]) | (tdd_sync_int & sync_source[1]) | tdd_sync_soft;
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endmodule
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