99 lines
4.1 KiB
Tcl
99 lines
4.1 KiB
Tcl
###############################################################################
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## Copyright (C) 2020-2024 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {num_cs 1} {num_sdi 1} {num_sdo 1} {sdi_delay 0} {echo_sclk 0} {cmd_mem_addr_width 4} {data_mem_addr_width 4} {sdi_fifo_addr_width 5} {sdo_fifo_addr_width 5} {sync_fifo_addr_width 4} {cmd_fifo_addr_width 4}} {
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puts "echo_sclk: $echo_sclk"
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create_bd_cell -type hier $name
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current_bd_instance /$name
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if {$async_spi_clk == 1} {
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create_bd_pin -dir I -type clk spi_clk
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}
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if {$echo_sclk == 1} {
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create_bd_pin -dir I -type clk echo_sclk
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}
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create_bd_pin -dir I -type clk clk
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create_bd_pin -dir I -type rst resetn
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create_bd_pin -dir I trigger
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create_bd_pin -dir O irq
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create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 m_spi
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_sample
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set execution "${name}_execution"
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set axi_regmap "${name}_axi_regmap"
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set offload "${name}_offload"
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set interconnect "${name}_interconnect"
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ad_ip_instance spi_engine_execution $execution
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ad_ip_parameter $execution CONFIG.DATA_WIDTH $data_width
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ad_ip_parameter $execution CONFIG.NUM_OF_CS $num_cs
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ad_ip_parameter $execution CONFIG.NUM_OF_SDI $num_sdi
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ad_ip_parameter $execution CONFIG.SDO_DEFAULT 1
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ad_ip_parameter $execution CONFIG.SDI_DELAY $sdi_delay
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ad_ip_parameter $execution CONFIG.ECHO_SCLK $echo_sclk
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ad_ip_instance axi_spi_engine $axi_regmap
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ad_ip_parameter $axi_regmap CONFIG.DATA_WIDTH $data_width
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ad_ip_parameter $axi_regmap CONFIG.NUM_OFFLOAD 1
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ad_ip_parameter $axi_regmap CONFIG.NUM_OF_SDI $num_sdi
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ad_ip_parameter $axi_regmap CONFIG.ASYNC_SPI_CLK $async_spi_clk
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ad_ip_parameter $axi_regmap CONFIG.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH $cmd_mem_addr_width
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ad_ip_parameter $axi_regmap CONFIG.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH $data_mem_addr_width
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ad_ip_parameter $axi_regmap CONFIG.SDI_FIFO_ADDRESS_WIDTH $sdi_fifo_addr_width
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ad_ip_parameter $axi_regmap CONFIG.SDO_FIFO_ADDRESS_WIDTH $sdo_fifo_addr_width
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ad_ip_parameter $axi_regmap CONFIG.SYNC_FIFO_ADDRESS_WIDTH $sync_fifo_addr_width
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ad_ip_parameter $axi_regmap CONFIG.CMD_FIFO_ADDRESS_WIDTH $cmd_fifo_addr_width
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ad_ip_instance spi_engine_offload $offload
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ad_ip_parameter $offload CONFIG.DATA_WIDTH $data_width
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ad_ip_parameter $offload CONFIG.ASYNC_SPI_CLK $async_spi_clk
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ad_ip_parameter $offload CONFIG.NUM_OF_SDI $num_sdi
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ad_ip_parameter $offload CONFIG.CMD_MEM_ADDRESS_WIDTH $cmd_mem_addr_width
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ad_ip_parameter $offload CONFIG.SDO_MEM_ADDRESS_WIDTH $data_mem_addr_width
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ad_ip_instance spi_engine_interconnect $interconnect
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ad_ip_parameter $interconnect CONFIG.DATA_WIDTH $data_width
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ad_ip_parameter $interconnect CONFIG.NUM_OF_SDI $num_sdi
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ad_connect $axi_regmap/spi_engine_offload_ctrl0 $offload/spi_engine_offload_ctrl
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ad_connect $offload/spi_engine_ctrl $interconnect/s0_ctrl
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ad_connect $axi_regmap/spi_engine_ctrl $interconnect/s1_ctrl
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ad_connect $interconnect/m_ctrl $execution/ctrl
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ad_connect $offload/offload_sdi m_axis_sample
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ad_connect $offload/trigger trigger
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ad_connect $execution/spi m_spi
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ad_connect clk $axi_regmap/s_axi_aclk
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if {$async_spi_clk == 1} {
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ad_connect spi_clk $offload/spi_clk
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ad_connect spi_clk $offload/ctrl_clk
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ad_connect spi_clk $execution/clk
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ad_connect spi_clk $axi_regmap/spi_clk
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ad_connect spi_clk $interconnect/clk
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} else {
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ad_connect clk $offload/spi_clk
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ad_connect clk $offload/ctrl_clk
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ad_connect clk $execution/clk
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ad_connect clk $axi_regmap/spi_clk
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ad_connect clk $interconnect/clk
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}
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if {$echo_sclk == 1} {
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ad_connect echo_sclk $execution/echo_sclk
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}
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ad_connect $axi_regmap/spi_resetn $offload/spi_resetn
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ad_connect $axi_regmap/spi_resetn $execution/resetn
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ad_connect $axi_regmap/spi_resetn $interconnect/resetn
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ad_connect resetn $axi_regmap/s_axi_aresetn
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ad_connect irq $axi_regmap/irq
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current_bd_instance /
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}
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