68 lines
2.3 KiB
Verilog
68 lines
2.3 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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reg clk = 1'b1;
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reg [3:0] reset_shift = 4'b1111;
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reg trigger_reset = 1'b0;
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wire reset;
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reg failed = 1'b0;
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initial
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begin
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if (VCD_FILE != "") begin
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$dumpfile (VCD_FILE);
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$dumpvars;
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end
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end
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always @(*) #10 clk <= ~clk;
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always @(posedge clk) begin
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if (trigger_reset == 1'b1) begin
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reset_shift <= 4'b1111;
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end else begin
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reset_shift <= {reset_shift[2:0],1'b0};
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end
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end
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assign reset = reset_shift[3];
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task do_trigger_reset;
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begin
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@(posedge clk) trigger_reset <= 1'b1;
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@(posedge clk) trigger_reset <= 1'b0;
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end
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endtask
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