119 lines
3.6 KiB
Verilog
119 lines
3.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module underflow_tb;
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parameter VCD_FILE = {`__FILE__,"cd"};
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parameter NUM_OF_CHANNELS = 8;
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parameter SAMPLES_PER_CHANNEL = 4;
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`include "tb_base.v"
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initial
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begin
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#1500000
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if (failed == 1'b0)
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$display("SUCCESS");
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else
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$display("FAILED");
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$finish;
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end
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localparam NUM_OF_PORTS = SAMPLES_PER_CHANNEL * NUM_OF_CHANNELS;
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reg fifo_rd_en = 1'b1;
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wire [NUM_OF_PORTS*8-1:0] fifo_rd_data;
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wire fifo_rd_valid;
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wire fifo_rd_underflow;
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reg s_axis_valid = 1'b1;
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wire s_axis_ready;
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reg [NUM_OF_PORTS*8-1:0] s_axis_data = {NUM_OF_PORTS*8{1'b1}};
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reg [NUM_OF_CHANNELS-1:0] enable = {NUM_OF_CHANNELS{1'b1}};
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integer counter = 0;
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always @(posedge clk) begin
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if (fifo_rd_underflow == 1'b1 && fifo_rd_data != 'h00) begin
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failed <= 1'b1;
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end
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if (fifo_rd_valid == 1'b1 && fifo_rd_data != {NUM_OF_PORTS*8{1'b1}}) begin
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failed <= 1'b1;
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end
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end
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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counter <= 0;
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s_axis_valid <= 1'b1;
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end else begin
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if (s_axis_valid == 1'b0) begin
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if (counter == 8) begin
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s_axis_valid <= 1'b1;
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end
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counter <= counter + 1;
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end else if (s_axis_ready == 1'b1) begin
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s_axis_valid <= 1'b0;
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counter <= 0;
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end
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end
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end
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always @(posedge clk) begin
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fifo_rd_en <= $random & 1;
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end
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util_upack2_impl #(
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.NUM_OF_CHANNELS(NUM_OF_CHANNELS),
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.SAMPLES_PER_CHANNEL(SAMPLES_PER_CHANNEL),
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.SAMPLE_DATA_WIDTH(8)
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) i_unpack (
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.clk(clk),
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.reset(reset),
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.enable(enable),
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.fifo_rd_en({NUM_OF_CHANNELS{fifo_rd_en}}),
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.fifo_rd_data(fifo_rd_data),
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.fifo_rd_valid(fifo_rd_valid),
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.fifo_rd_underflow(fifo_rd_underflow),
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.s_axis_valid(s_axis_valid),
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.s_axis_ready(s_axis_ready),
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.s_axis_data(s_axis_data));
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endmodule
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