91 lines
3.5 KiB
Tcl
91 lines
3.5 KiB
Tcl
###############################################################################
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## Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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# ad7768 interface
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create_bd_port -dir I clk_in
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create_bd_port -dir I ready_in
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create_bd_port -dir I -from 7 -to 0 data_in
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# instances
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ad_ip_instance axi_dmac ad7768_dma
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ad_ip_parameter ad7768_dma CONFIG.DMA_TYPE_SRC 2
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ad_ip_parameter ad7768_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter ad7768_dma CONFIG.CYCLIC 0
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ad_ip_parameter ad7768_dma CONFIG.SYNC_TRANSFER_START 1
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ad_ip_parameter ad7768_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter ad7768_dma CONFIG.AXI_SLICE_DEST 0
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ad_ip_parameter ad7768_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter ad7768_dma CONFIG.DMA_DATA_WIDTH_SRC 32
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ad_ip_instance axi_dmac ad7768_dma_2
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ad_ip_parameter ad7768_dma_2 CONFIG.DMA_TYPE_SRC 2
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ad_ip_parameter ad7768_dma_2 CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter ad7768_dma_2 CONFIG.CYCLIC 0
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ad_ip_parameter ad7768_dma_2 CONFIG.SYNC_TRANSFER_START 1
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ad_ip_parameter ad7768_dma_2 CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter ad7768_dma_2 CONFIG.AXI_SLICE_DEST 0
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ad_ip_parameter ad7768_dma_2 CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter ad7768_dma_2 CONFIG.DMA_DATA_WIDTH_SRC 256
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# ps7-hp1
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ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP1 1
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# parallel path channel pack
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ad_ip_instance util_cpack2 util_ad7768_adc_pack
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ad_ip_parameter util_ad7768_adc_pack CONFIG.NUM_OF_CHANNELS 8
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ad_ip_parameter util_ad7768_adc_pack CONFIG.SAMPLE_DATA_WIDTH 32
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# axi_ad7768
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ad_ip_instance axi_ad7768 axi_ad7768_adc
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ad_ip_parameter axi_ad7768_adc CONFIG.NUM_CHANNELS 8
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for {set i 0} {$i < 8} {incr i} {
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ad_connect axi_ad7768_adc/adc_enable_$i util_ad7768_adc_pack/enable_$i
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ad_connect axi_ad7768_adc/adc_data_$i util_ad7768_adc_pack/fifo_wr_data_$i
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}
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ad_connect axi_ad7768_adc/s_axi_aclk sys_ps7/FCLK_CLK0
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ad_connect axi_ad7768_adc/clk_in clk_in
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ad_connect axi_ad7768_adc/ready_in ready_in
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ad_connect axi_ad7768_adc/data_in data_in
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ad_connect axi_ad7768_adc/adc_valid util_ad7768_adc_pack/fifo_wr_en
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ad_connect axi_ad7768_adc/adc_clk util_ad7768_adc_pack/clk
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ad_connect axi_ad7768_adc/adc_reset util_ad7768_adc_pack/reset
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ad_connect axi_ad7768_adc/adc_dovf util_ad7768_adc_pack/fifo_wr_overflow
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#serial DMA
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ad_connect ad7768_dma/m_dest_axi_aresetn sys_cpu_resetn
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ad_connect ad7768_dma/fifo_wr_clk axi_ad7768_adc/adc_clk
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ad_connect ad7768_dma/fifo_wr_en axi_ad7768_adc/adc_valid
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ad_connect ad7768_dma/fifo_wr_din axi_ad7768_adc/adc_data
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ad_connect ad7768_dma/fifo_wr_sync axi_ad7768_adc/adc_sync
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#parallel DMA
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ad_connect ad7768_dma_2/m_dest_axi_aresetn sys_cpu_resetn
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ad_connect ad7768_dma_2/fifo_wr_clk axi_ad7768_adc/adc_clk
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ad_connect ad7768_dma_2/fifo_wr util_ad7768_adc_pack/packed_fifo_wr
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# interrupts
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ad_cpu_interrupt ps-13 mb-13 ad7768_dma/irq
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ad_cpu_interrupt ps-10 mb-10 ad7768_dma_2/irq
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# cpu / memory interconnects
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ad_cpu_interconnect 0x7C400000 ad7768_dma
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ad_cpu_interconnect 0x7C480000 ad7768_dma_2
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ad_cpu_interconnect 0x43c00000 axi_ad7768_adc
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ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect sys_cpu_clk ad7768_dma/m_dest_axi
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ad_mem_hp1_interconnect sys_cpu_clk ad7768_dma_2/m_dest_axi
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