182 lines
5.3 KiB
Verilog
182 lines
5.3 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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input [12:0] gpio_bd_i,
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output [ 7:0] gpio_bd_o,
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input ref_clk0_p,
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input ref_clk0_n,
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input sysref_p,
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input sysref_n,
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input [ 3:0] rx_data_p,
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input [ 3:0] rx_data_n,
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input [ 1:0] rx_dummy_p,
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input [ 1:0] rx_dummy_n,
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output rx_sync0_p,
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output rx_sync0_n,
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output rx_sync1_p,
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output rx_sync1_n,
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output spi_csn,
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output spi_clk,
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output spi_mosi,
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input spi_miso,
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inout fda,
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inout fdb,
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inout pwdn,
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output pmod_spi_csn,
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output pmod_spi_mosi,
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input pmod_spi_miso,
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output pmod_spi_clk
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);
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// internal signals
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wire [94:0] gpio_i;
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wire [94:0] gpio_o;
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wire [94:0] gpio_t;
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wire [20:0] gpio_bd;
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wire ref_clk0;
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wire rx_sync;
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wire rx_ref_core_clk0_s;
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wire rx_ref_core_clk0;
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wire [2:0] spi0_csn;
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wire [2:0] spi1_csn;
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wire sysref_s;
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wire sysref_0;
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assign gpio_i[94:35] = gpio_o[94:35];
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assign gpio_i[31:21] = gpio_o[31:21];
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assign gpio_i[ 7: 0] = gpio_o[ 7: 0];
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assign gpio_i[20: 8] = gpio_bd_i;
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assign gpio_bd_o = gpio_o[7:0];
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assign spi_csn = spi0_csn[0];
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assign pmod_spi_csn = spi1_csn[0];
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// instantiations
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ad_iobuf #(
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.DATA_WIDTH(3)
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) i_iobuf (
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.dio_t ({gpio_t[34:32]}),
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.dio_i ({gpio_o[34:32]}),
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.dio_o ({gpio_i[34:32]}),
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.dio_p ({fdb, // 34
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fda, // 33
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pwdn})); // 32
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IBUFDS_GTE4 i_ibufds_ref_clk0 (
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.CEB (1'd0),
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.I (ref_clk0_p),
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.IB (ref_clk0_n),
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.O (ref_clk0),
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.ODIV2 (rx_ref_core_clk0_s));
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BUFG_GT i_bufg_gt_ref_core_clk(
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.I(rx_ref_core_clk0_s),
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.CE (1'b1),
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.CEMASK(1'b1),
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.CLR (1'b0),
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.CLRMASK(1'b1),
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.DIV (3'b000),
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.O(rx_ref_core_clk0));
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IBUFDS_GTE4 i_ibufds_sysref (
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.CEB (1'd0),
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.I (sysref_p),
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.IB (sysref_n),
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.O (),
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.ODIV2 (sysref_s));
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BUFG_GT i_bufg_gt_sysref(
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.I(sysref_s),
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.CE (1'b1),
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.CEMASK(1'b1),
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.CLR (1'b0),
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.CLRMASK(1'b1),
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.DIV (3'b000),
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.O(sysref_0));
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OBUFDS i_obufds_rx_sync0 (
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.I (rx_sync),
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.O (rx_sync0_p),
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.OB (rx_sync0_n));
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OBUFDS i_obufds_rx_sync1 (
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.I (rx_sync),
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.O (rx_sync1_p),
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.OB (rx_sync1_n));
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system_wrapper i_system_wrapper (
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.rx_data_0_n (rx_data_n[0]),
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.rx_data_0_p (rx_data_p[0]),
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.rx_data_1_n (rx_data_n[1]),
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.rx_data_1_p (rx_data_p[1]),
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.rx_data_2_n (rx_dummy_n[0]),
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.rx_data_2_p (rx_dummy_p[0]),
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.rx_data_3_n (rx_dummy_n[1]),
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.rx_data_3_p (rx_dummy_p[1]),
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.rx_data_4_n (rx_data_n[2]),
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.rx_data_4_p (rx_data_p[2]),
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.rx_data_5_n (rx_data_n[3]),
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.rx_data_5_p (rx_data_p[3]),
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.rx_ref_clk_0 (ref_clk0),
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.rx_core_clk_0 (rx_ref_core_clk0),
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.rx_sync_0 (rx_sync),
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.rx_sysref_0 (sysref_0),
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.spi0_csn (spi0_csn),
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.spi0_miso (spi_miso),
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.spi0_mosi (spi_mosi),
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.spi0_sclk (spi_clk),
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.spi1_csn (spi1_csn),
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.spi1_miso (pmod_spi_miso),
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.spi1_mosi (pmod_spi_mosi),
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.spi1_sclk (pmod_spi_clk));
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endmodule
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