294 lines
8.7 KiB
Verilog
294 lines
8.7 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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inout [14:0] ddr_addr,
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inout [ 2:0] ddr_ba,
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inout ddr_cas_n,
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inout ddr_ck_n,
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inout ddr_ck_p,
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inout ddr_cke,
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inout ddr_cs_n,
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inout [ 3:0] ddr_dm,
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inout [31:0] ddr_dq,
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inout [ 3:0] ddr_dqs_n,
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inout [ 3:0] ddr_dqs_p,
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inout ddr_odt,
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inout ddr_ras_n,
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inout ddr_reset_n,
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inout ddr_we_n,
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inout fixed_io_ddr_vrn,
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inout fixed_io_ddr_vrp,
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inout [53:0] fixed_io_mio,
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inout fixed_io_ps_clk,
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inout fixed_io_ps_porb,
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inout fixed_io_ps_srstb,
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inout [31:0] gpio_bd,
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output hdmi_out_clk,
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output hdmi_vsync,
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output hdmi_hsync,
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output hdmi_data_e,
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output [15:0] hdmi_data,
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output i2s_mclk,
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output i2s_bclk,
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output i2s_lrclk,
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output i2s_sdata_out,
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input i2s_sdata_in,
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output spdif,
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inout iic_scl,
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inout iic_sda,
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inout [ 1:0] iic_mux_scl,
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inout [ 1:0] iic_mux_sda,
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input otg_vbusoc,
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// mii interface
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output reset_a,
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output mdc_fmc_a,
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inout mdio_fmc_a,
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input [ 3:0] mii_rxd_a,
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input mii_rx_dv_a,
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input mii_rx_er_a,
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input mii_rx_clk_a,
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output [ 3:0] mii_txd_a,
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output mii_tx_en_a,
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input mii_tx_clk_a,
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input mii_crs_a,
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input link_st_a,
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input led_0_a,
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output reset_b,
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output mdc_fmc_b,
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inout mdio_fmc_b,
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input [ 3:0] mii_rxd_b,
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input mii_rx_dv_b,
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input mii_rx_er_b,
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input mii_rx_clk_b,
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output [ 3:0] mii_txd_b,
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output mii_tx_en_b,
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input mii_tx_clk_b,
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input mii_crs_b,
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input link_st_b,
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input led_0_b,
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// LEDs
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output led_ar_c_c2m,
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output led_ar_a_c2m,
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output led_al_c_c2m,
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output led_al_a_c2m,
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output led_br_c_c2m,
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output led_br_a_c2m,
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output led_bl_c_c2m,
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output led_bl_a_c2m
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);
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// internal signals
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wire reset;
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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wire [ 1:0] iic_mux_scl_i_s;
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wire [ 1:0] iic_mux_scl_o_s;
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wire iic_mux_scl_t_s;
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wire [ 1:0] iic_mux_sda_i_s;
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wire [ 1:0] iic_mux_sda_o_s;
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wire iic_mux_sda_t_s;
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wire [ 3:0] mii_txd_extra_a;
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wire [ 3:0] mii_txd_extra_b;
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assign reset_a = reset;
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assign reset_b = reset;
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// port a - right led (activity/status) yellow only
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assign led_ar_c_c2m = led_0_a;
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assign led_ar_a_c2m = 1'b0;
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// port a - left led (speed mode) hard-coded to 100M=yellow no feedback from mac
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assign led_al_c_c2m = 1'b1;
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assign led_al_a_c2m = 1'b0;
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// port b - right led (activity/status) yellow only
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assign led_br_c_c2m = led_0_b;
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assign led_br_a_c2m = 1'b0;
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// port b - left led (speed mode) hard-coded to 100M=yellow no feedback from mac
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assign led_bl_c_c2m = 1'b1;
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assign led_bl_a_c2m = 1'b0;
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assign gpio_i[63:36] = gpio_o[63:36];
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assign gpio_i[33:32] = gpio_o[33:32];
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assign gpio_i[35] = link_st_a;
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assign gpio_i[34] = link_st_b;
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ad_iobuf #(
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.DATA_WIDTH(32)
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) i_iobuf_bd (
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.dio_t (gpio_t[31:0]),
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.dio_i (gpio_o[31:0]),
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.dio_o (gpio_i[31:0]),
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.dio_p (gpio_bd));
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ad_iobuf #(
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.DATA_WIDTH(2)
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) i_iobuf_iic_scl (
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.dio_t ({iic_mux_scl_t_s,iic_mux_scl_t_s}),
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.dio_i (iic_mux_scl_o_s),
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.dio_o (iic_mux_scl_i_s),
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.dio_p (iic_mux_scl));
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ad_iobuf #(
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.DATA_WIDTH(2)
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) i_iobuf_iic_sda (
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.dio_t ({iic_mux_sda_t_s,iic_mux_sda_t_s}),
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.dio_i (iic_mux_sda_o_s),
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.dio_o (iic_mux_sda_i_s),
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.dio_p (iic_mux_sda));
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// instantiations
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system_wrapper i_system_wrapper (
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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.ddr_ck_n (ddr_ck_n),
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.ddr_ck_p (ddr_ck_p),
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.ddr_cke (ddr_cke),
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.ddr_cs_n (ddr_cs_n),
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.ddr_dm (ddr_dm),
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.ddr_dq (ddr_dq),
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.ddr_dqs_n (ddr_dqs_n),
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.ddr_dqs_p (ddr_dqs_p),
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.ddr_odt (ddr_odt),
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.ddr_ras_n (ddr_ras_n),
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.ddr_reset_n (ddr_reset_n),
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.ddr_we_n (ddr_we_n),
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.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
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.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
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.fixed_io_mio (fixed_io_mio),
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.fixed_io_ps_clk (fixed_io_ps_clk),
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.fixed_io_ps_porb (fixed_io_ps_porb),
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.fixed_io_ps_srstb (fixed_io_ps_srstb),
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.hdmi_data (hdmi_data),
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.hdmi_data_e (hdmi_data_e),
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.hdmi_hsync (hdmi_hsync),
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.hdmi_out_clk (hdmi_out_clk),
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.hdmi_vsync (hdmi_vsync),
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.i2s_bclk (i2s_bclk),
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.i2s_lrclk (i2s_lrclk),
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.i2s_mclk (i2s_mclk),
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.i2s_sdata_in (i2s_sdata_in),
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.i2s_sdata_out (i2s_sdata_out),
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.iic_fmc_scl_io (iic_scl),
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.iic_fmc_sda_io (iic_sda),
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.iic_mux_scl_i (iic_mux_scl_i_s),
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.iic_mux_scl_o (iic_mux_scl_o_s),
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.iic_mux_scl_t (iic_mux_scl_t_s),
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.iic_mux_sda_i (iic_mux_sda_i_s),
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.iic_mux_sda_o (iic_mux_sda_o_s),
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.iic_mux_sda_t (iic_mux_sda_t_s),
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.otg_vbusoc (otg_vbusoc),
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.spdif (spdif),
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.spi0_clk_i (1'b0),
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.spi0_clk_o (),
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.spi0_csn_0_o (),
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.spi0_csn_1_o (),
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.spi0_csn_2_o (),
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.spi0_csn_i (1'b1),
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.spi0_sdi_i (1'b0),
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.spi0_sdo_i (1'b0),
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.spi0_sdo_o (),
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.spi1_clk_i (1'b0),
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.spi1_clk_o (),
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.spi1_csn_0_o (),
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.spi1_csn_1_o (),
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.spi1_csn_2_o (),
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.spi1_csn_i (1'b1),
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.spi1_sdi_i (1'b0),
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.spi1_sdo_i (1'b0),
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.spi1_sdo_o (),
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.reset (reset),
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.GMII_ETHERNET_0_0_col(led_0_a),
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.GMII_ETHERNET_0_0_crs(mii_crs_a),
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.GMII_ETHERNET_0_0_rx_clk(mii_rx_clk_a),
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.GMII_ETHERNET_0_0_rx_dv(mii_rx_dv_a),
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.GMII_ETHERNET_0_0_rx_er(mii_rx_er_a),
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.GMII_ETHERNET_0_0_rxd({4'h0,mii_rxd_a}),
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.GMII_ETHERNET_0_0_tx_clk(mii_tx_clk_a),
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.GMII_ETHERNET_0_0_tx_en(mii_tx_en_a),
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.GMII_ETHERNET_0_0_tx_er(),
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.GMII_ETHERNET_0_0_txd({mii_txd_extra_a,mii_txd_a}),
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.MDIO_ETHERNET_0_0_mdc(mdc_fmc_a),
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.MDIO_ETHERNET_0_0_mdio_io(mdio_fmc_a),
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.GMII_ETHERNET_1_0_col(led_0_b),
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.GMII_ETHERNET_1_0_crs(mii_crs_b),
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.GMII_ETHERNET_1_0_rx_clk(mii_rx_clk_b),
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.GMII_ETHERNET_1_0_rx_dv(mii_rx_dv_b),
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.GMII_ETHERNET_1_0_rx_er(mii_rx_er_b),
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.GMII_ETHERNET_1_0_rxd({4'h0,mii_rxd_b}),
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.GMII_ETHERNET_1_0_tx_clk(mii_tx_clk_b),
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.GMII_ETHERNET_1_0_tx_en(mii_tx_en_b),
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.GMII_ETHERNET_1_0_tx_er(),
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.GMII_ETHERNET_1_0_txd({mii_txd_extra_b,mii_txd_b}),
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.MDIO_ETHERNET_1_0_mdc(mdc_fmc_b),
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.MDIO_ETHERNET_1_0_mdio_io(mdio_fmc_b));
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endmodule
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