118 lines
3.8 KiB
Verilog
Executable File
118 lines
3.8 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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input sys_clk_n,
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input sys_clk_p,
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output ddr4_act_n,
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output [16:0] ddr4_adr,
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output [ 1:0] ddr4_ba,
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output [ 1:0] ddr4_bg,
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output ddr4_ck_c,
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output ddr4_ck_t,
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output ddr4_cke,
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output ddr4_cs_n,
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inout [ 7:0] ddr4_dm_n,
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inout [63:0] ddr4_dq,
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inout [ 7:0] ddr4_dqs_c,
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inout [ 7:0] ddr4_dqs_t,
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output ddr4_odt,
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output ddr4_reset_n,
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output [ 3:0] gpio_led,
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input [ 3:0] gpio_dip_sw,
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input [ 1:0] gpio_pb
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);
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// internal signals
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wire [95:0] gpio_i;
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wire [95:0] gpio_o;
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wire [95:0] gpio_t;
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// Board GPIOS. Buttons, LEDs, etc...
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assign gpio_led = gpio_o[3:0];
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assign gpio_i[3:0] = gpio_o[3:0];
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assign gpio_i[7:4] = gpio_dip_sw;
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assign gpio_i[9:8] = gpio_pb;
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// Unused GPIOs
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assign gpio_i[95:64] = gpio_o[95:64];
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assign gpio_i[63:32] = gpio_o[63:32];
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assign gpio_i[31:10] = gpio_o[31:10];
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system_wrapper i_system_wrapper (
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.gpio0_i (gpio_i[31:0]),
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.gpio0_o (gpio_o[31:0]),
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.gpio0_t (gpio_t[31:0]),
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.gpio1_i (gpio_i[63:32]),
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.gpio1_o (gpio_o[63:32]),
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.gpio1_t (gpio_t[63:32]),
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.gpio2_i (gpio_i[95:64]),
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.gpio2_o (gpio_o[95:64]),
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.gpio2_t (gpio_t[95:64]),
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.ddr4_dimm1_sma_clk_clk_n (sys_clk_n),
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.ddr4_dimm1_sma_clk_clk_p (sys_clk_p),
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.ddr4_dimm1_act_n (ddr4_act_n),
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.ddr4_dimm1_adr (ddr4_adr),
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.ddr4_dimm1_ba (ddr4_ba),
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.ddr4_dimm1_bg (ddr4_bg),
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.ddr4_dimm1_ck_c (ddr4_ck_c),
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.ddr4_dimm1_ck_t (ddr4_ck_t),
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.ddr4_dimm1_cke (ddr4_cke),
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.ddr4_dimm1_cs_n (ddr4_cs_n),
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.ddr4_dimm1_dm_n (ddr4_dm_n),
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.ddr4_dimm1_dq (ddr4_dq),
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.ddr4_dimm1_dqs_c (ddr4_dqs_c),
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.ddr4_dimm1_dqs_t (ddr4_dqs_t),
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.ddr4_dimm1_odt (ddr4_odt),
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.ddr4_dimm1_reset_n (ddr4_reset_n),
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.spi0_csn (),
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.spi0_miso (1'b0),
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.spi0_mosi (),
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.spi0_sclk (),
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.spi1_csn (),
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.spi1_miso (1'b0),
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.spi1_mosi (),
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.spi1_sclk ());
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endmodule
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