167 lines
6.5 KiB
Verilog
Executable File
167 lines
6.5 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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input sys_clk_n,
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input sys_clk_p,
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output [ 5:0] ch0_lpddr4_trip1_ca_a,
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output [ 5:0] ch0_lpddr4_trip1_ca_b,
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output ch0_lpddr4_trip1_ck_c_a,
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output ch0_lpddr4_trip1_ck_c_b,
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output ch0_lpddr4_trip1_ck_t_a,
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output ch0_lpddr4_trip1_ck_t_b,
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output ch0_lpddr4_trip1_cke_a,
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output ch0_lpddr4_trip1_cke_b,
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output ch0_lpddr4_trip1_cs_a,
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output ch0_lpddr4_trip1_cs_b,
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inout [ 1:0] ch0_lpddr4_trip1_dmi_a,
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inout [ 1:0] ch0_lpddr4_trip1_dmi_b,
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inout [15:0] ch0_lpddr4_trip1_dq_a,
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inout [15:0] ch0_lpddr4_trip1_dq_b,
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inout [ 1:0] ch0_lpddr4_trip1_dqs_c_a,
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inout [ 1:0] ch0_lpddr4_trip1_dqs_c_b,
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inout [ 1:0] ch0_lpddr4_trip1_dqs_t_a,
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inout [ 1:0] ch0_lpddr4_trip1_dqs_t_b,
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output ch0_lpddr4_trip1_reset_n,
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output [ 5:0] ch1_lpddr4_trip1_ca_a,
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output [ 5:0] ch1_lpddr4_trip1_ca_b,
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output ch1_lpddr4_trip1_ck_c_a,
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output ch1_lpddr4_trip1_ck_c_b,
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output ch1_lpddr4_trip1_ck_t_a,
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output ch1_lpddr4_trip1_ck_t_b,
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output ch1_lpddr4_trip1_cke_a,
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output ch1_lpddr4_trip1_cke_b,
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output ch1_lpddr4_trip1_cs_a,
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output ch1_lpddr4_trip1_cs_b,
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inout [ 1:0] ch1_lpddr4_trip1_dmi_a,
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inout [ 1:0] ch1_lpddr4_trip1_dmi_b,
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inout [15:0] ch1_lpddr4_trip1_dq_a,
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inout [15:0] ch1_lpddr4_trip1_dq_b,
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inout [ 1:0] ch1_lpddr4_trip1_dqs_c_a,
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inout [ 1:0] ch1_lpddr4_trip1_dqs_c_b,
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inout [ 1:0] ch1_lpddr4_trip1_dqs_t_a,
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inout [ 1:0] ch1_lpddr4_trip1_dqs_t_b,
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output ch1_lpddr4_trip1_reset_n,
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// GPIOs
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output [ 3:0] gpio_led,
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input [ 3:0] gpio_dip_sw,
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input [ 1:0] gpio_pb
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);
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// internal signals
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wire [95:0] gpio_i;
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wire [95:0] gpio_o;
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wire [95:0] gpio_t;
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// Board GPIOS. Buttons, LEDs, etc...
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assign gpio_led = gpio_o[3:0];
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assign gpio_i[3:0] = gpio_o[3:0];
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assign gpio_i[7:4] = gpio_dip_sw;
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assign gpio_i[9:8] = gpio_pb;
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// Unused GPIOs
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assign gpio_i[95:64] = gpio_o[95:64];
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assign gpio_i[63:32] = gpio_o[63:32];
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assign gpio_i[31:10] = gpio_o[31:10];
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system_wrapper i_system_wrapper (
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.gpio0_i (gpio_i[31:0]),
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.gpio0_o (gpio_o[31:0]),
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.gpio0_t (gpio_t[31:0]),
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.gpio1_i (gpio_i[63:32]),
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.gpio1_o (gpio_o[63:32]),
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.gpio1_t (gpio_t[63:32]),
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.gpio2_i (gpio_i[95:64]),
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.gpio2_o (gpio_o[95:64]),
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.gpio2_t (gpio_t[95:64]),
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.lpddr4_clk1_clk_n (sys_clk_n),
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.lpddr4_clk1_clk_p (sys_clk_p),
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.ch0_lpddr4_trip1_ca_a (ch0_lpddr4_trip1_ca_a),
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.ch0_lpddr4_trip1_ca_b (ch0_lpddr4_trip1_ca_b),
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.ch0_lpddr4_trip1_ck_c_a (ch0_lpddr4_trip1_ck_c_a),
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.ch0_lpddr4_trip1_ck_c_b (ch0_lpddr4_trip1_ck_c_b),
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.ch0_lpddr4_trip1_ck_t_a (ch0_lpddr4_trip1_ck_t_a),
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.ch0_lpddr4_trip1_ck_t_b (ch0_lpddr4_trip1_ck_t_b),
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.ch0_lpddr4_trip1_cke_a (ch0_lpddr4_trip1_cke_a),
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.ch0_lpddr4_trip1_cke_b (ch0_lpddr4_trip1_cke_b),
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.ch0_lpddr4_trip1_cs_a (ch0_lpddr4_trip1_cs_a),
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.ch0_lpddr4_trip1_cs_b (ch0_lpddr4_trip1_cs_b),
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.ch0_lpddr4_trip1_dmi_a (ch0_lpddr4_trip1_dmi_a),
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.ch0_lpddr4_trip1_dmi_b (ch0_lpddr4_trip1_dmi_b),
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.ch0_lpddr4_trip1_dq_a (ch0_lpddr4_trip1_dq_a),
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.ch0_lpddr4_trip1_dq_b (ch0_lpddr4_trip1_dq_b),
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.ch0_lpddr4_trip1_dqs_c_a (ch0_lpddr4_trip1_dqs_c_a),
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.ch0_lpddr4_trip1_dqs_c_b (ch0_lpddr4_trip1_dqs_c_b),
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.ch0_lpddr4_trip1_dqs_t_a (ch0_lpddr4_trip1_dqs_t_a),
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.ch0_lpddr4_trip1_dqs_t_b (ch0_lpddr4_trip1_dqs_t_b),
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.ch0_lpddr4_trip1_reset_n (ch0_lpddr4_trip1_reset_n),
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.ch1_lpddr4_trip1_ca_a (ch1_lpddr4_trip1_ca_a),
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.ch1_lpddr4_trip1_ca_b (ch1_lpddr4_trip1_ca_b),
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.ch1_lpddr4_trip1_ck_c_a (ch1_lpddr4_trip1_ck_c_a),
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.ch1_lpddr4_trip1_ck_c_b (ch1_lpddr4_trip1_ck_c_b),
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.ch1_lpddr4_trip1_ck_t_a (ch1_lpddr4_trip1_ck_t_a),
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.ch1_lpddr4_trip1_ck_t_b (ch1_lpddr4_trip1_ck_t_b),
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.ch1_lpddr4_trip1_cke_a (ch1_lpddr4_trip1_cke_a),
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.ch1_lpddr4_trip1_cke_b (ch1_lpddr4_trip1_cke_b),
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.ch1_lpddr4_trip1_cs_a (ch1_lpddr4_trip1_cs_a),
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.ch1_lpddr4_trip1_cs_b (ch1_lpddr4_trip1_cs_b),
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.ch1_lpddr4_trip1_dmi_a (ch1_lpddr4_trip1_dmi_a),
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.ch1_lpddr4_trip1_dmi_b (ch1_lpddr4_trip1_dmi_b),
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.ch1_lpddr4_trip1_dq_a (ch1_lpddr4_trip1_dq_a),
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.ch1_lpddr4_trip1_dq_b (ch1_lpddr4_trip1_dq_b),
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.ch1_lpddr4_trip1_dqs_c_a (ch1_lpddr4_trip1_dqs_c_a),
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.ch1_lpddr4_trip1_dqs_c_b (ch1_lpddr4_trip1_dqs_c_b),
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.ch1_lpddr4_trip1_dqs_t_a (ch1_lpddr4_trip1_dqs_t_a),
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.ch1_lpddr4_trip1_dqs_t_b (ch1_lpddr4_trip1_dqs_t_b),
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.ch1_lpddr4_trip1_reset_n (ch1_lpddr4_trip1_reset_n),
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.spi0_csn (),
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.spi0_miso (1'b0),
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.spi0_mosi (),
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.spi0_sclk (),
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.spi1_csn (),
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.spi1_miso (1'b0),
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.spi1_mosi (),
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.spi1_sclk ());
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endmodule
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