223 lines
9.3 KiB
Tcl
223 lines
9.3 KiB
Tcl
###############################################################################
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## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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create_bd_port -dir O -from 2 -to 0 spi0_csn
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create_bd_port -dir O spi0_sclk
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create_bd_port -dir O spi0_mosi
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create_bd_port -dir I spi0_miso
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create_bd_port -dir O -from 2 -to 0 spi1_csn
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create_bd_port -dir O spi1_sclk
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create_bd_port -dir O spi1_mosi
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create_bd_port -dir I spi1_miso
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create_bd_port -dir I -from 31 -to 0 gpio0_i
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create_bd_port -dir O -from 31 -to 0 gpio0_o
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create_bd_port -dir O -from 31 -to 0 gpio0_t
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create_bd_port -dir I -from 31 -to 0 gpio1_i
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create_bd_port -dir O -from 31 -to 0 gpio1_o
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create_bd_port -dir O -from 31 -to 0 gpio1_t
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create_bd_port -dir I -from 31 -to 0 gpio2_i
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create_bd_port -dir O -from 31 -to 0 gpio2_o
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create_bd_port -dir O -from 31 -to 0 gpio2_t
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# instance: versal_cips and NoC
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ad_ip_instance versal_cips sys_cips
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apply_bd_automation -rule xilinx.com:bd_rule:cips -config { \
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board_preset {Yes} \
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boot_config {Custom} \
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configure_noc {Add new AXI NoC} \
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debug_config {JTAG} \
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design_flow {Full System} \
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mc_type {LPDDR} \
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num_mc_ddr {None} \
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num_mc_lpddr {1} \
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pl_clocks {2} \
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pl_resets {1} \
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} [get_bd_cells sys_cips]
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set_property -dict [list \
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CONFIG.CLOCK_MODE {Custom} \
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CONFIG.CPM_CONFIG { \
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CPM_PCIE0_MODES {None} \
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} \
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CONFIG.DEVICE_INTEGRITY_MODE {Custom} \
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CONFIG.IO_CONFIG_MODE {Custom} \
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CONFIG.PS_PL_CONNECTIVITY_MODE {Custom} \
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CONFIG.PS_PMC_CONFIG { \
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CLOCK_MODE {Custom} \
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DDR_MEMORY_MODE {Connectivity to DDR via NOC} \
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DEBUG_MODE {JTAG} \
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DESIGN_MODE {1} \
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DEVICE_INTEGRITY_MODE {Sysmon temperature voltage and external IO monitoring} \
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IO_CONFIG_MODE {Custom} \
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PMC_CRP_PL0_REF_CTRL_FREQMHZ {100} \
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PMC_GPIO0_MIO_PERIPHERAL {{ENABLE 1} {IO {PMC_MIO 0 .. 25}}} \
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PMC_GPIO1_MIO_PERIPHERAL {{ENABLE 1} {IO {PMC_MIO 26 .. 51}}} \
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PMC_MIO37 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA high} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \
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PMC_QSPI_FBCLK {{ENABLE 1} {IO {PMC_MIO 6}}} \
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PMC_QSPI_PERIPHERAL_DATA_MODE {x4} \
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PMC_QSPI_PERIPHERAL_ENABLE {1} \
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PMC_QSPI_PERIPHERAL_MODE {Dual Parallel} \
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PMC_REF_CLK_FREQMHZ {33.3333} \
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PMC_SD1 {{CD_ENABLE 1} {CD_IO {PMC_MIO 28}} {POW_ENABLE 1} {POW_IO {PMC_MIO 51}} {RESET_ENABLE 0} {RESET_IO {PMC_MIO 12}} {WP_ENABLE 0} {WP_IO {PMC_MIO 1}}} \
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PMC_SD1_PERIPHERAL {{CLK_100_SDR_OTAP_DLY 0x3} {CLK_200_SDR_OTAP_DLY 0x2} {CLK_50_DDR_ITAP_DLY 0x2A} {CLK_50_DDR_OTAP_DLY 0x3} {CLK_50_SDR_ITAP_DLY 0x25} {CLK_50_SDR_OTAP_DLY 0x4} {ENABLE 1} {IO {PMC_MIO 26 .. 36}}} \
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PMC_SD1_SLOT_TYPE {SD 3.0 AUTODIR} \
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PMC_USE_PMC_NOC_AXI0 {1} \
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PS_BOARD_INTERFACE {ps_pmc_fixed_io} \
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PS_ENET0_MDIO {{ENABLE 1} {IO {PS_MIO 24 .. 25}}} \
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PS_ENET0_PERIPHERAL {{ENABLE 1} {IO {PS_MIO 0 .. 11}}} \
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PS_GEN_IPI0_ENABLE {1} \
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PS_GEN_IPI0_MASTER {A72} \
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PS_GEN_IPI1_ENABLE {1} \
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PS_GEN_IPI2_ENABLE {1} \
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PS_GEN_IPI3_ENABLE {1} \
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PS_GEN_IPI4_ENABLE {1} \
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PS_GEN_IPI5_ENABLE {1} \
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PS_GEN_IPI6_ENABLE {1} \
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PS_GPIO_EMIO_PERIPHERAL_ENABLE {1} \
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PS_HSDP_EGRESS_TRAFFIC {JTAG} \
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PS_HSDP_INGRESS_TRAFFIC {JTAG} \
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PS_HSDP_MODE {NONE} \
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PS_I2C0_PERIPHERAL {{ENABLE 1} {IO {PMC_MIO 46 .. 47}}} \
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PS_I2C1_PERIPHERAL {{ENABLE 1} {IO {PMC_MIO 44 .. 45}}} \
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PS_I2CSYSMON_PERIPHERAL {{ENABLE 0} {IO {PMC_MIO 39 .. 40}}} \
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PS_IRQ_USAGE {{CH0 1} {CH1 1} {CH10 1} {CH11 1} {CH12 1} {CH13 1} {CH14 1} {CH15 1} {CH2 1} {CH3 1} {CH4 1} {CH5 1} {CH6 1} {CH7 1} {CH8 1} {CH9 1}} \
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PS_MIO7 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL disable} {SCHMITT 0} {SLEW slow} {USAGE Reserved}} \
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PS_MIO9 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL disable} {SCHMITT 0} {SLEW slow} {USAGE Reserved}} \
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PS_NUM_FABRIC_RESETS {1} \
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PS_PCIE_EP_RESET1_IO {PS_MIO 18} \
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PS_PCIE_EP_RESET2_IO {PS_MIO 19} \
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PS_PCIE_RESET {ENABLE 1} \
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PS_PL_CONNECTIVITY_MODE {Custom} \
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PS_SPI0 {{GRP_SS0_ENABLE 1} {GRP_SS0_IO {EMIO}} {GRP_SS1_ENABLE 1} {GRP_SS1_IO {EMIO}} {GRP_SS2_ENABLE 1} {GRP_SS2_IO {EMIO}} {PERIPHERAL_ENABLE 1} {PERIPHERAL_IO EMIO}} \
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PS_SPI1 {{GRP_SS0_ENABLE 1} {GRP_SS0_IO {EMIO}} {GRP_SS1_ENABLE 1} {GRP_SS1_IO {EMIO}} {GRP_SS2_ENABLE 1} {GRP_SS2_IO {EMIO}} {PERIPHERAL_ENABLE 1} {PERIPHERAL_IO EMIO}} \
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PS_UART0_PERIPHERAL {{ENABLE 1} {IO {PMC_MIO 42 .. 43}}} \
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PS_USB3_PERIPHERAL {{ENABLE 1} {IO {PMC_MIO 13 .. 25}}} \
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PS_USE_FPD_CCI_NOC {1} \
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PS_USE_FPD_CCI_NOC0 {1} \
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PS_USE_M_AXI_FPD {1} \
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PS_USE_NOC_LPD_AXI0 {1} \
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PS_USE_PMCPL_CLK0 {1} \
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PS_USE_PMCPL_CLK1 {1} \
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SMON_ALARMS {Set_Alarms_On} \
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SMON_ENABLE_TEMP_AVERAGING {0} \
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SMON_INTERFACE_TO_USE {I2C} \
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SMON_MEAS126 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 0} {MODE {2 V unipolar}} {NAME VCCAUX} {SUPPLY_NUM 0}} \
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SMON_MEAS127 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 0} {MODE {2 V unipolar}} {NAME VCCAUX_PMC} {SUPPLY_NUM 1}} \
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SMON_MEAS148 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 0} {MODE {2 V unipolar}} {NAME VCC_PMC} {SUPPLY_NUM 2}} \
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SMON_MEAS149 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 0} {MODE {2 V unipolar}} {NAME VCC_PSFP} {SUPPLY_NUM 3}} \
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SMON_MEAS150 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 0} {MODE {2 V unipolar}} {NAME VCC_PSLP} {SUPPLY_NUM 4}} \
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SMON_MEAS152 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 0} {MODE {2 V unipolar}} {NAME VCC_SOC} {SUPPLY_NUM 5}} \
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SMON_MEAS153 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 0} {MODE {2 V unipolar}} {NAME VP_VN} {SUPPLY_NUM 6}} \
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SMON_PMBUS_ADDRESS {0x18} \
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SMON_TEMP_AVERAGING_SAMPLES {0} \
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} \
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CONFIG.PS_PMC_CONFIG_APPLIED {1} \
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] [get_bd_cells sys_cips]
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set_property -dict [list \
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CONFIG.MC_CHANNEL_INTERLEAVING {true} \
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CONFIG.MC_CH_INTERLEAVING_SIZE {256_Bytes} \
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] [get_bd_cells axi_noc_0]
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ad_ip_instance proc_sys_reset sys_rstgen
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ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1
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ad_ip_instance proc_sys_reset sys_350m_rstgen
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ad_ip_parameter sys_350m_rstgen CONFIG.C_EXT_RST_WIDTH 1
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# system reset/clock definitions
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ad_connect sys_cpu_clk sys_cips/pl0_ref_clk
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ad_connect sys_350m_clk sys_cips/pl1_ref_clk
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ad_connect sys_cips/pl0_resetn sys_rstgen/ext_reset_in
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ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
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ad_connect sys_cips/pl0_resetn sys_350m_rstgen/ext_reset_in
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ad_connect sys_350m_clk sys_350m_rstgen/slowest_sync_clk
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ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
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ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
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ad_connect sys_350m_reset sys_350m_rstgen/peripheral_reset
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ad_connect sys_350m_resetn sys_350m_rstgen/peripheral_aresetn
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# gpio
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ad_connect gpio0_i sys_cips/lpd_gpio_i
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ad_connect gpio0_o sys_cips/lpd_gpio_o
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ad_connect gpio0_t sys_cips/lpd_gpio_t
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# gpio extension witn 64 IOs
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ad_ip_instance axi_gpio axi_gpio
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ad_ip_parameter axi_gpio CONFIG.C_IS_DUAL 1
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ad_ip_parameter axi_gpio CONFIG.C_GPIO_WIDTH 32
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ad_ip_parameter axi_gpio CONFIG.C_GPIO2_WIDTH 32
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ad_ip_parameter axi_gpio CONFIG.C_INTERRUPT_PRESENT 1
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ad_connect gpio1_i axi_gpio/gpio_io_i
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ad_connect gpio1_o axi_gpio/gpio_io_o
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ad_connect gpio1_t axi_gpio/gpio_io_t
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ad_connect gpio2_i axi_gpio/gpio2_io_i
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ad_connect gpio2_o axi_gpio/gpio2_io_o
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ad_connect gpio2_t axi_gpio/gpio2_io_t
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## generic system clocks&resets pointers
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set sys_cpu_clk [get_bd_nets sys_cpu_clk]
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set sys_dma_clk [get_bd_nets sys_350m_clk]
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set sys_cpu_reset [get_bd_nets sys_cpu_reset]
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set sys_cpu_resetn [get_bd_nets sys_cpu_resetn]
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set sys_dma_reset [get_bd_nets sys_350m_reset]
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set sys_dma_resetn [get_bd_nets sys_350m_resetn]
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# spi
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ad_ip_instance xlconcat spi0_csn_sources
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ad_ip_parameter spi0_csn_sources config.num_ports {3}
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ad_connect spi0_csn_sources/dout spi0_csn
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ad_connect sys_cips/spi0_sck_o spi0_sclk
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ad_connect sys_cips/spi0_sck_i GND
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ad_connect sys_cips/spi0_io0_o spi0_mosi
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ad_connect sys_cips/spi0_io0_i spi0_miso
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ad_connect sys_cips/spi0_io1_i GND
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ad_connect sys_cips/spi0_ss_o spi0_csn_sources/in0
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ad_connect sys_cips/spi0_ss1_o spi0_csn_sources/in1
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ad_connect sys_cips/spi0_ss2_o spi0_csn_sources/in2
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ad_connect sys_cips/spi0_ss_i VCC
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ad_ip_instance xlconcat spi1_csn_sources
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ad_ip_parameter spi1_csn_sources config.num_ports {3}
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ad_connect spi1_csn_sources/dout spi1_csn
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ad_connect sys_cips/spi1_sck_o spi1_sclk
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ad_connect sys_cips/spi1_sck_i GND
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ad_connect sys_cips/spi1_io0_o spi1_mosi
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ad_connect sys_cips/spi1_io0_i spi1_miso
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ad_connect sys_cips/spi1_io1_i GND
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ad_connect sys_cips/spi1_ss_o spi1_csn_sources/in0
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ad_connect sys_cips/spi1_ss1_o spi1_csn_sources/in1
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ad_connect sys_cips/spi1_ss2_o spi1_csn_sources/in2
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ad_connect sys_cips/spi1_ss_i VCC
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# system id
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ad_ip_instance axi_sysid axi_sysid_0
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ad_ip_instance sysid_rom rom_sys_0
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ad_connect axi_sysid_0/rom_addr rom_sys_0/rom_addr
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ad_connect axi_sysid_0/sys_rom_data rom_sys_0/rom_data
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ad_connect sys_cpu_clk rom_sys_0/clk
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# interconnect
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ad_cpu_interconnect 0x44000000 axi_gpio
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ad_cpu_interconnect 0x45000000 axi_sysid_0
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# interrupts
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ad_cpu_interrupt ps-0 mb-xx axi_gpio/ip2intc_irpt
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