155 lines
4.6 KiB
Verilog
155 lines
4.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ns
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module prcfg_adc #(
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parameter CHANNEL_ID = 0,
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parameter DATA_WIDTH = 32) (
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input clk,
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// control ports
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input [31:0] control,
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output reg [31:0] status,
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// FIFO interface
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input src_adc_valid,
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input [(DATA_WIDTH-1):0] src_adc_data,
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input src_adc_enable,
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output reg dst_adc_valid,
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output reg [(DATA_WIDTH-1):0] dst_adc_data,
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output reg dst_adc_enable);
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localparam SYMBOL_WIDTH = 2;
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localparam RP_ID = 8'hA2;
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reg [ 7:0] adc_pn_data = 'hF1;
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reg [ 3:0] mode = 'h0;
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reg [ 3:0] channel_sel = 'h0;
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wire adc_valid;
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wire [(SYMBOL_WIDTH-1):0] adc_data_s;
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wire [ 7:0] adc_pn_data_s;
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wire adc_pn_err_s;
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wire adc_pn_oos_s;
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// prbs function
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function [ 7:0] pn;
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input [ 7:0] din;
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reg [ 7:0] dout;
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begin
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dout[7] = din[6];
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dout[6] = din[5];
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dout[5] = din[4];
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dout[4] = din[3];
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dout[3] = din[2];
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dout[2] = din[1];
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dout[1] = din[7] ^ din[4];
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dout[0] = din[6] ^ din[3];
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pn = dout;
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end
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endfunction
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// update control and status registers
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always @(posedge clk) begin
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channel_sel <= control[ 3:0];
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mode <= control[ 7:4];
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end
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assign adc_valid = src_adc_valid & src_adc_enable;
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assign adc_pn_data_s = (adc_pn_oos_s == 1'b1) ? {adc_pn_data[7:2], adc_data_s} : adc_pn_data;
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ad_pnmon #(
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.DATA_WIDTH(8)
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) i_pn_mon (
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.adc_clk(clk),
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.adc_valid_in(adc_valid),
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.adc_data_in({adc_pn_data[7:2], adc_data_s}),
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.adc_data_pn(adc_pn_data_s),
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.adc_pn_oos(adc_pn_oos_s),
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.adc_pn_err(adc_pn_err_s));
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// prbs generation
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always @(posedge clk) begin
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if(adc_valid == 1'b1) begin
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adc_pn_data <= pn(adc_pn_data);
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end
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end
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// qpsk demodulator
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qpsk_demod i_qpsk_demod1 (
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.clk(clk),
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.data_qpsk_i(src_adc_data[15: 0]),
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.data_qpsk_q(src_adc_data[31:16]),
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.data_valid(adc_valid),
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.data_output(adc_data_s)
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);
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// output logic for data ans status
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always @(posedge clk) begin
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dst_adc_valid <= src_adc_valid;
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dst_adc_enable <= src_adc_enable;
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case(mode)
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4'h0 : begin
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dst_adc_data <= src_adc_data;
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end
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4'h1 : begin
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dst_adc_data <= 32'h0;
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end
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4'h2 : begin
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dst_adc_data <= {30'h0, adc_data_s};
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end
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default : begin
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dst_adc_data <= src_adc_data;
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end
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endcase
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if((mode == 3'd2) && (channel_sel == CHANNEL_ID)) begin
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status <= {22'h0, adc_pn_err_s, adc_pn_oos_s, RP_ID};
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end else begin
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status <= {24'h0, RP_ID};
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end
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end
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endmodule
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