69 lines
2.5 KiB
Verilog
69 lines
2.5 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ns
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module qpsk_demod (
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input clk,
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input [15:0] data_qpsk_i,
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input [15:0] data_qpsk_q,
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input data_valid,
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output [ 1:0] data_output);
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wire [15:0] filtered_data_i;
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wire [15:0] filtered_data_q;
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wire [ 7:0] demodulated_data;
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// output logic
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assign data_output = demodulated_data[1:0];
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// instantiation
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Raised_Cosine_Receive_Filter i_rx_filter (
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.clk(clk),
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.reset(1'b0),
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.enb_1_1_1(data_valid),
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.In1_re(data_qpsk_i),
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.In1_im(data_qpsk_q),
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.Out1_re(filtered_data_i),
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.Out1_im(filtered_data_q)
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);
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QPSK_Demodulator_Baseband i_qpsk_demod(
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.in0_re(filtered_data_i),
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.in0_im(filtered_data_q),
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.out0(demodulated_data)
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);
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endmodule
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