pluto_hdl_adi/library/axi_ad9361
Istvan Csomortani 6b90054343 axi_ad9361: Define CDC constraint for tdd_sync 2017-02-24 11:24:07 +02:00
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altera altera- cmos cores 2016-10-31 13:13:48 -04:00
xilinx xilinx/axi_ad9361_lvds_if: Remove ila 2016-10-11 18:13:45 +03:00
Makefile updated makefiles 2016-12-09 23:06:41 +02:00
axi_ad9361.v Fix warnings 2016-11-14 15:17:15 +02:00
axi_ad9361_constr.sdc library/axi_ad9361: tdd false paths 2016-05-04 13:42:12 -04:00
axi_ad9361_constr.xdc axi_ad9361: Define CDC constraint for tdd_sync 2017-02-24 11:24:07 +02:00
axi_ad9361_hw.tcl alt_serdes- a10 ddio fixes 2016-11-01 12:41:25 -04:00
axi_ad9361_ip.tcl axi_ad9361: Grup interfaces to add support for more carriers 2016-10-11 17:58:49 +03:00
axi_ad9361_rx.v axi_ad9361: Add DRP connection to the interface module 2016-10-11 17:59:12 +03:00
axi_ad9361_rx_channel.v ad9361- adc data path split 2016-09-23 13:42:14 -04:00
axi_ad9361_rx_pnmon.v hdl/library: Update the IP parameters 2015-08-19 14:11:47 +03:00
axi_ad9361_tdd.v axi_ad9361_tdd: Register the tdd_sync_cntr output 2017-02-23 11:31:23 +02:00
axi_ad9361_tdd_if.v hdl/library: Update the IP parameters 2015-08-19 14:11:47 +03:00
axi_ad9361_tx.v ad9361- dac data path split 2016-09-23 16:13:46 -04:00
axi_ad9361_tx_channel.v ad9361- dac data path split 2016-09-23 16:13:46 -04:00