Istvan Csomortani ac2e5a9dac constraints: Update constraints ... Xilinx recommends that all synchronizer flip-flops have their ASYNC_REG property set to true in order to preserve the synchronizer cells through any logic optimization during synthesis and implementation.		2017-02-24 13:43:32 +02:00
..
Makefile	updated makefiles	2016-12-09 23:06:41 +02:00
util_dacfifo.v	adc/dac- fifo constraints	2016-08-11 10:00:41 -04:00
util_dacfifo_constr.xdc	constraints: Update constraints	2017-02-24 13:43:32 +02:00
util_dacfifo_ip.tcl	util_dacfifo: Add constraints file	2016-04-12 13:21:50 +03:00