270 lines
7.3 KiB
Verilog
270 lines
7.3 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// This is the dac physical interface (drives samples from the low speed clock to the
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// dac clock domain.
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`timescale 1ns/100ps
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module axi_ad9122_if (
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// dac interface
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dac_clk_in_p,
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dac_clk_in_n,
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dac_clk_out_p,
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dac_clk_out_n,
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dac_frame_out_p,
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dac_frame_out_n,
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dac_data_out_p,
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dac_data_out_n,
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// internal resets and clocks
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dac_rst,
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dac_clk,
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dac_div_clk,
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dac_status,
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// data interface
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dac_frame_i0,
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dac_data_i0,
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dac_frame_i1,
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dac_data_i1,
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dac_frame_i2,
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dac_data_i2,
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dac_frame_i3,
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dac_data_i3,
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dac_frame_q0,
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dac_data_q0,
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dac_frame_q1,
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dac_data_q1,
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dac_frame_q2,
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dac_data_q2,
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dac_frame_q3,
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dac_data_q3,
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// mmcm reset
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mmcm_rst,
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// drp interface
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up_clk,
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up_rstn,
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up_drp_sel,
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up_drp_wr,
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up_drp_addr,
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up_drp_wdata,
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up_drp_rdata,
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up_drp_ready,
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up_drp_locked);
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// parameters
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parameter PCORE_DEVICE_TYPE = 0;
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parameter PCORE_SERDES_DDR_N = 1;
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parameter PCORE_MMCM_BUFIO_N = 1;
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parameter PCORE_IODELAY_GROUP = "dac_if_delay_group";
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// dac interface
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input dac_clk_in_p;
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input dac_clk_in_n;
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output dac_clk_out_p;
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output dac_clk_out_n;
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output dac_frame_out_p;
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output dac_frame_out_n;
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output [15:0] dac_data_out_p;
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output [15:0] dac_data_out_n;
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// internal resets and clocks
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input dac_rst;
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output dac_clk;
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output dac_div_clk;
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output dac_status;
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// data interface
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input dac_frame_i0;
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input [15:0] dac_data_i0;
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input dac_frame_i1;
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input [15:0] dac_data_i1;
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input dac_frame_i2;
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input [15:0] dac_data_i2;
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input dac_frame_i3;
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input [15:0] dac_data_i3;
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input dac_frame_q0;
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input [15:0] dac_data_q0;
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input dac_frame_q1;
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input [15:0] dac_data_q1;
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input dac_frame_q2;
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input [15:0] dac_data_q2;
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input dac_frame_q3;
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input [15:0] dac_data_q3;
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// mmcm reset
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input mmcm_rst;
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// drp interface
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input up_clk;
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input up_rstn;
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input up_drp_sel;
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input up_drp_wr;
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input [11:0] up_drp_addr;
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input [15:0] up_drp_wdata;
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output [15:0] up_drp_rdata;
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output up_drp_ready;
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output up_drp_locked;
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// internal registers
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reg dac_status_m1 = 'd0;
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reg dac_status = 'd0;
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// dac status
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always @(posedge dac_div_clk) begin
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if (dac_rst == 1'b1) begin
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dac_status_m1 <= 1'd0;
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dac_status <= 1'd0;
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end else begin
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dac_status_m1 <= up_drp_locked;
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dac_status <= dac_status_m1;
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end
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end
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// dac data output serdes(s) & buffers
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ad_serdes_out #(
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.DEVICE_TYPE (PCORE_DEVICE_TYPE),
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.SERDES(PCORE_SERDES_DDR_N),
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.DATA_WIDTH(16))
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i_serdes_out_data (
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.rst (dac_rst),
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.clk (dac_clk),
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.div_clk (dac_div_clk),
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.data_s0 (dac_data_i0),
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.data_s1 (dac_data_q0),
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.data_s2 (dac_data_i1),
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.data_s3 (dac_data_q1),
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.data_s4 (dac_data_i2),
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.data_s5 (dac_data_q2),
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.data_s6 (dac_data_i3),
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.data_s7 (dac_data_q3),
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.data_out_p (dac_data_out_p),
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.data_out_n (dac_data_out_n));
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// dac frame output serdes & buffer
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ad_serdes_out #(
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.DEVICE_TYPE (PCORE_DEVICE_TYPE),
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.SERDES(PCORE_SERDES_DDR_N),
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.DATA_WIDTH(1))
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i_serdes_out_frame (
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.rst (dac_rst),
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.clk (dac_clk),
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.div_clk (dac_div_clk),
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.data_s0 (dac_frame_i0),
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.data_s1 (dac_frame_q0),
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.data_s2 (dac_frame_i1),
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.data_s3 (dac_frame_q1),
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.data_s4 (dac_frame_i2),
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.data_s5 (dac_frame_q2),
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.data_s6 (dac_frame_i3),
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.data_s7 (dac_frame_q3),
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.data_out_p (dac_frame_out_p),
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.data_out_n (dac_frame_out_n));
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// dac clock output serdes & buffer
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ad_serdes_out #(
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.DEVICE_TYPE (PCORE_DEVICE_TYPE),
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.SERDES(PCORE_SERDES_DDR_N),
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.DATA_WIDTH(1))
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i_serdes_out_clk (
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.rst (dac_rst),
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.clk (dac_clk),
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.div_clk (dac_div_clk),
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.data_s0 (1'b1),
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.data_s1 (1'b0),
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.data_s2 (1'b1),
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.data_s3 (1'b0),
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.data_s4 (1'b1),
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.data_s5 (1'b0),
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.data_s6 (1'b1),
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.data_s7 (1'b0),
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.data_out_p (dac_clk_out_p),
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.data_out_n (dac_clk_out_n));
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// dac clock input buffers
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ad_serdes_clk #(
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.SERDES (PCORE_SERDES_DDR_N),
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.MMCM (PCORE_MMCM_BUFIO_N),
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.MMCM_DEVICE_TYPE (PCORE_DEVICE_TYPE),
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.MMCM_CLKIN_PERIOD (1.667),
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.MMCM_VCO_DIV (6),
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.MMCM_VCO_MUL (12),
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.MMCM_CLK0_DIV (2),
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.MMCM_CLK1_DIV (8))
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i_serdes_clk (
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.mmcm_rst (mmcm_rst),
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.clk_in_p (dac_clk_in_p),
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.clk_in_n (dac_clk_in_n),
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.clk (dac_clk),
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.div_clk (dac_div_clk),
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.up_clk (up_clk),
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.up_rstn (up_rstn),
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.up_drp_sel (up_drp_sel),
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.up_drp_wr (up_drp_wr),
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.up_drp_addr (up_drp_addr),
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.up_drp_wdata (up_drp_wdata),
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.up_drp_rdata (up_drp_rdata),
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.up_drp_ready (up_drp_ready),
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.up_drp_locked (up_drp_locked));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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