0108d01043
Add a wrapper that instantiates the Arria10 Native PHY and configures it for JESD204 operation. The datapath width is set to 4 octets per beat. The maximum lane rate that is achievable with hard-logic PCS included in the PHY is below the requirements of the JESD204 for some of the PHY speed grades. For projects that require a lane rate that is higher than what the hard-logic PCS can support a soft-logic PCS module can be instantiated. The external interface of the jesd204_phy is identical regardless of whether soft- or hard-logic PCS is used. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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| README.md | ||
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