Lars-Peter Clausen 0108d01043 library: Add JESD204 PHY wrapper for Arria10 Native PHY ... Add a wrapper that instantiates the Arria10 Native PHY and configures it for JESD204 operation. The datapath width is set to 4 octets per beat. The maximum lane rate that is achievable with hard-logic PCS included in the PHY is below the requirements of the JESD204 for some of the PHY speed grades. For projects that require a lane rate that is higher than what the hard-logic PCS can support a soft-logic PCS module can be instantiated. The external interface of the jesd204_phy is identical regardless of whether soft- or hard-logic PCS is used. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>		2017-08-21 11:20:57 +02:00
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avl_adxcfg	avl_adxcfg: Consistently use non-blocking assignments	2017-07-24 16:06:00 +02:00
avl_adxcvr	avl_adxcvr: Perform octet order swap	2017-08-03 17:57:58 +02:00
avl_adxcvr_octet_swap	avl_adxcvr: Perform octet order swap	2017-08-03 17:57:58 +02:00
avl_adxphy	avl_adxcvr: Simplify TX lane mapping	2017-08-03 17:57:58 +02:00
avl_dacfifo	avl_dacfifo: Fix timing violation	2017-06-07 11:02:44 +01:00
axi_adxcvr	axi_adxcvr: Avoid implicit signal truncation warning	2017-08-07 17:42:17 +02:00
common	alt_mem_asym: Set read latency to 1 clock cycle	2017-08-13 10:28:11 +02:00
jesd204_phy	library: Add JESD204 PHY wrapper for Arria10 Native PHY	2017-08-21 11:20:57 +02:00